Senior Physical Design Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

T HE ROLE:

In this role you will be given an opportunity to work on the next  generation  technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets.  The DXIO FEINT/Implementation team  is responsible for  Synthesis , place & Route,  Timing closure/CDC/LINT/ DFx  for  very high  speed (>2G) design with complex I/O clocking.

THE PERSON:

As a  Design  Engineer, you will be working with a diverse team  of  physical design  engineers,  RTL  design engineers,  and managers from   NBIO  IP team .  You will drive physical implementation of IP  through the entire physical design flow to achieve  best  PPA , while shortening the  overall  development schedule .   This role  provide s  an excellent growth opportunity for robust individuals  looking to make a  difference.  This is an exciting time to join the AMD team!

KEY RESPONSIBILITIES:

- Looking for an experienced   Design  Engineer who will  focus  on all   physical  implementation aspects of next generation IPs. Th is   team  deal s  with multiple I/O protocols including PCIe, SATA,  Ethernet   & Infinity  Fabric link-layer.
- This team is a group of highly experienced ASIC design engineers working on High speed (>2G) designs with very complex  clocking infrastructures. The team owns implementation activities including  Synthesis   & DF T , floorplan ,  placement, clock tree synthesis,  routing ,  STA  closure .
- The team will work on  cutting edge  IP for  these I /O  protocols  to  achieve physical  implementation  with best PPA ,  including   developing reference   floorplans , implementation scripts  for  SoCs  worldwide ,  and  support  SoC s worldwide .

PREFERRED EXPERIENCE:

- Industry experience  in  Synthesis, Floor-planning,  Place ment ,  clock trees synthesis,  Post  Route  Timing  closure  for  high-speed > =2 GHz  designs.
- CDC, PTPX, STA, LINT & DF T,  IP, Physical design flow & scripting in TCL, Python

ACADEMIC CREDENTIALS:

- B . E .  or M.E  in Electrical or Computer Engineering (or equivalent)

LOCATION: Markham, Vancouver

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Benefits offered are described:  AMD benefits at a glance .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.