About this role
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google (https://www.google.com/about/careers/applications/benefits/).
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 4 years of experience working with verification methodologies and languages, including SystemVerilog and UVM.
- Experience with interconnect protocols such as AXI, APB, and ACE.
- Experience building and maintaining verification test benches, test cases, and test environments.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience managing the full verification life cycle, from initial test planning through coverage closure.
- Expertise in advanced verification methodologies and techniques (including UVM, formal verification, and UPF-based power simulations) to ensure bug-free silicon in complex SoCs.
- Strong problem-solving and communication skills, with the ability to collaborate effectively in a team setting.
- Plan verification strategies for complex digital design blocks by thoroughly understanding design specifications and collaborating with design engineers to identify critical verification scenarios.
- Build constrained-random verification environments utilizing SystemVerilog and Universal Verification Methodology (UVM).
- Define and implement comprehensive coverage metrics targeting stimulus and corner cases.
- Debug test failures alongside design engineers to ensure functionally correct design blocks.
- Achieve coverage closure to identify verification gaps and demonstrate progress toward tape-out.