DDR Validation Engineer

## Company:
QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA

## Job Area:
Engineering Group, Engineering Group > ASICS Engineering

General Summary:

About the Team

Qualcomm’s System Validation & Emulation (SVE) team is part of the central SoC validation organization responsible for ensuring end-to-end silicon quality across pre- and post-silicon phases .

This team focuses on content quality and system-level validation enablement , offering deep exposure to Qualcomm SoCs through bare-metal validation content , scalable automation frameworks, and complex system debugs. Engineers in this role work across HW and SW boundaries to develop, validate, and scale system-level test content , ensuring high-quality silicon validation across a wide range of SoC domains.

Excellent Opportunity to work on cutting-edge SoCs across multiple product segments , including:

- Premium mobile and flagship platforms
- Data center
- AI Accelerator platform

Role Overview

Seeking an experienced DDR Validation Engineer for end-to-end validation of next-generation LPDDR5X and LPDDR6 memory subsystems on AI Accelerator and Flagship mobile platforms.  This role will lead memory bring-up, performance validation, system stress, debug, and production readiness from pre-silicon through post-silicon phases.

Key Responsibilities

- Define and execute DDR validation strategy across emulation, FPGA, and silicon platforms.
- Drive LPDDR5X/LPDDR6 bring-up, training validation, frequency scaling, low-power state validation, and feature enablement.
- Develop and execute validation plans covering memory functionality, performance, reliability, power, and corner-case scenarios.
- Lead debug of DDR controller, PHY, firmware, SI/PI, timing, and system-level issues.
- Validate interactions between DDR, CPU, GPU, NPU, cache hierarchy, NoC, and system software.
- Drive bandwidth, latency, QoS, memory pressure, and AI workload characterization.
- Develop scalable automation, regression infrastructure, and debug analytics frameworks.
- Partner with Architecture, Design, Firmware, SI/PI, Package, and DRAM vendors to root-cause and resolve issues.

Required Qualifications

- BS/MS/PhD in EE, CE, CS, or related field.
- 5+ years of experience in DDR/memory subsystem validation or silicon bring-up.
- Strong understanding of: LPDDR4/5/5X/6 architectures
- DDR controllers and PHYs
- Memory training and calibration algorithms
- Cache, coherency, and NoC architectures
- Power management and low-power memory features

- Strong post-silicon debug experience.
- Proficiency in C/C++ and low-level software development.

Preferred Qualifications

- Mobile SoC, AI compute, automotive, or server platform validation experience.
- Familiarity with SI/PI analysis, memory performance tuning, and thermal characterization.
- Experience driving first-silicon memory bring-up and volume production qualification.

Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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