About this role
What will your job look like?
- Define, implement and enhance verification environments using UVM methodology.
- Write and debug tests that combine UVM methodology and SW code.
- Identify and write various types of coverage measures.
- Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
- Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs.
All you need is:
- BSc in electrical engineering, computer engineering, or computer science
- 8+ years of experience working in verification environment, tests, and test bench development (SV/UVM/C/C++)
- System Verilog writing skills, preferably in OVM/UVM
- SW embedded experience, C/C++ skills
- TestPlan defining and Coverage-Driven Verification experience
- 3rd-party IPs integration testing experience
- Waveform debugging with the latest EDA tools, root-cause bugs independently
- Skills in scripting Perl/Python - Advantage
- Knowledge in Industry Standard protocols such as AXI/OCP/APB - Advantage
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