About this role
<b>Overview</b><br><div><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. </span></p></div><div><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Microsoft's Hardware Systems organization is developing AI-native silicon and hyperscale systems designed to power the next generation of frontier AI models. The MAIA platform combines custom silicon, high-performance networking, advanced compiler technologies, and large-scale system infrastructure to enable industry-leading AI training and inference. </span></p></div><div><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">The Platform Systems Engineering (PSE) team is seeking a Sr. AI Accelerator Tools Development Engineer to lead the development of next-generation stress, validation, and performance tooling for MAIA AI accelerator platforms. </span></p></div><div><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">In this role, you will build software frameworks, stress workloads, and validation tools that exercise every layer of the AI stack, from hardware execution engines and memory subsystems to compiler-generated kernels, distributed communication fabrics, and large-scale AI workloads. Your work will play a critical role in platform bring-up, qualification, performance characterization, reliability validation, and fleet readiness for both current and future generations of MAIA systems. </span></p></div><div><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">You will work closely with silicon architects, compiler teams, runtime developers, performance engineers, validation teams, and AI framework developers to translate platform requirements into scalable tooling and workload solutions. </span></p><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. </span></p></div><div> </div><br><br><b>Responsibilities</b><br><div><div><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">AI Workload & Stress Tool Development </span></p></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Design and develop scalable stress, performance, and validation frameworks for MAIA AI accelerator platforms. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Build workload generation infrastructure capable of exercising compute, memory, interconnect, networking, storage, and system-level resources. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Develop reusable stress tools using PyTorch, Triton, Python, C++, and custom MAIA SDKs. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Create synthetic and production-inspired workloads that model training and inference behaviors observed in large-scale AI deployments. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Build automated infrastructure for workload deployment, orchestration, telemetry collection, and result analysis. </span></p></li></ul></div><div><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Hardware-Aware Workload Optimization </span></p></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Develop and optimize kernels targeting custom AI accelerators. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Create GEMM, attention, collective communication, and memory intensive stress workloads. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Analyze execution behavior across the hardware-software stack and identify bottlenecks impacting utilization and performance. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Collaborate with compiler and runtime teams to improve workload efficiency and hardware utilization. </span></p></li></ul></div><div><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Compiler & SDK Integration </span></p></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Develop tooling that integrates with MAIA compiler pipelines, SDKs, runtime environments, and performance analysis tools. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Understand and debug compiler output, generated kernels, scheduling decisions, and execution behavior. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Build automation around model compilation, kernel validation, regression testing, and workload portability. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Partner with compiler teams to validate new compiler features and workload optimization strategies. </span></p></li></ul></div><div><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Platform Validation & Reliability </span></p></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Design workload suites for platform bring-up, qualification, and reliability testing. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Build comprehensive regression infrastructure supporting silicon, firmware, system software, and platform releases. </span></p></li></ul></div></div><div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Develop automated validation tools capable of identifying correctness, performance, thermal, power, and stability issues. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Enable platform readiness through scalable validation methodologies and continuous regression testing. </span></p></li></ul></div><div><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Performance Engineering </span></p></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Characterize system performance across compute, networking, memory, and storage subsystems. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Develop benchmarking methodologies and performance dashboards. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Adapt and optimize industry-standard workloads including: </span></p></li></ul></div><div><ul style="list-style-type:circle"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">HPL/HPC benchmarks </span></p></li></ul></div><div><ul style="list-style-type:circle"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">LLM training workloads </span></p></li></ul></div><div><ul style="list-style-type:circle"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Transformer-based inference workloads </span></p></li></ul></div><div><ul style="list-style-type:circle"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Collective communication benchmarks </span></p></li></ul></div><div><ul style="list-style-type:circle"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">AI framework benchmark suites </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Drive root-cause analysis and optimization initiatives across the stack. </span></p></li></ul></div><div><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Developer Productivity & Automation </span></p></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Improve developer productivity through automation, CI/CD integration, diagnostics, and debugging infrastructure. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Build reusable tooling for workload generation, failure triage, telemetry analysis, and reporting. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Develop dashboards and automated workflows for large-scale validation environments. </span></p></li></ul></div><div><ul style="list-style-type:disc"><li style="font-family:arial, helvetica, sans-serif;font-size:10.0pt"><p><span style="font-family:arial, helvetica, sans-serif;font-size:10.0pt">Partner with engineering teams to convert recurring validation challenges into durable tooling solutions. </span></p></li></ul></div></div><br><br><b>Qualifications</b><br><div><div><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;"><strong>Required Qualifications:</strong></span></p><ul><li><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;">Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience </span><ul><li><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;">OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience </span></li><li><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;">OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience </span></li><li><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;">OR equivalent experience.</span></li></ul></li><li><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;">4+ years of experience with programming skills in C/C++ and Python, with experience designing and developing production-quality software systems, frameworks, runtimes, or infrastructure.</span></li><li><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;">4+ years of experience developing, debugging, or optimizing AI workloads for GPUs, AI accelerators, or HPC systems, including experience with PyTorch or comparable AI frameworks and compute-intensive kernels.</span></li><li><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;">4+ years of experience with accelerator architecture and performance optimization, including compute engines, memory hierarchy, interconnects, runtime systems, performance profiling, bottleneck analysis, and debugging across hardware/software boundaries.</span></li></ul><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;"> </span></p><div><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;"><strong>Other Qualifications:</strong></span></div><div> </div><div><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;">Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:</span></div><div> </div><div><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;">Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. </span></li></ul><p> </p></div></div></div><div><div><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;"><strong>Preferred Qualifications: </strong></span></p></div><div><ul style="list-style-type: disc;"><li style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;"><div>Experience with custom AI accelerator SDKs, compiler ecosystems, kernel generation frameworks, or code-generation pipelines, including technologies such as LLVM, MLIR, or Triton.</div></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;"><div>Experience developing or optimizing AI training and inference workloads, including LLMs and other large-scale AI models.</div></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;"><div>Experience with collective communication libraries, high-performance networking, distributed AI systems, or performance characterization of large-scale AI clusters.</div></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;"><div>Experience with CI/CD systems, containerized environments, automated testing, or cloud-scale validation infrastructure.</div></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;"><div>Experience working with silicon bring-up or post-silicon validation teams.</div></li></ul></div></div><div><p> </p><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;">#azure #MAIA #AI/ML</span></p></div> <br><br><p>Firmware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year. </p><p></p> <p>Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:<br><a href="https://careers.microsoft.com/us/en/us-corporate-pay">https://careers.microsoft.com/us/en/us-corporate-pay</a></p><br><p>This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.</p><br><hr><br><p>Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about <a href="https://careers.microsoft.com/v2/global/en/accessibility.html"><b><u>requesting accommodations.</u></b></a></p>