Senior Analog/Mixed-Signal Layout Engineer - SERDES

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THE ROLE:

As a member of SERDES Group, you will help develop layout designs. As a member of the team, you will work closely with the architecture, IP design, Physical Design teams to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

- Implementation Layout of blocks and macros

- Own and deliver the high-quality macros with help of team
- Mentor and groom the juniors in the team
- Work with contractor team and the planned work done as per aligned schedule
- Enable release flows as required

PREFERRED EXPERIENCE:

- 8+ yrs of hands-on experience in layout design
- Experience with Cadence virtuoso, Caliber and other verification tools as required for layout development
- Preferrable experience in high speed SERDES blocks

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in Electrical Engineering or equivalent

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Benefits offered are described:  AMD benefits at a glance .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.