About this role
Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers to help prove the correctness of the Nuvacore CPU. As part of the design verification (DV) team, you will help verify by building the test plans, environments, and checkers that find deep bugs in the pipeline long before silicon, working shoulder-to-shoulder with architecture and RTL design.
THE ROLE
Plan & Strategy: Drive the verification scope, strategy, and test plans for the CPU at unit and/or top level of the CPU design.
Environment Setup: Build, maintain, and scale robust verification environments — stimulus generators, checkers, transactors, and coverage — that exercise the pipeline end to end.
Test & Debug: Generate complex directed and random tests in assembly, C, or random instruction sequences (RIS) to expose corner cases such as speculation, hazards, flushes, and retirement ordering.
Performance Verification: Partner with architects to correlate RTL against performance models, hunting throughput, stall, and branch-prediction-accuracy issues.
Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.
Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up
MINIMUM REQUIREMENTS
Minimum of BS + 0 years relevant industry experience.
REQUIREMENTS — NICE TO HAVE
Strong background in computer architecture and digital logic design fundamentals
Experience in Verilog or SystemVerilog, with practical experience in digital simulation and debugging
Hands-on experience with Python, Perl, or other scripting languages for testbench automation
Proven ability to work independently and drive tasks to completion
Familiarity with C/C++ or assembly language programming is highly desirable
Strong interpersonal and communication skills with a drive to tackle complex, diverse engineering challenges
