FE Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work with other specialists that are members of the SoC Design, Soc Design Verification, System Verification, STA, and Physical Design teams to implement designs/flows for sophisticated Socs. Integrate various IPs and ensure design meets DFT (design-for-test), CDC (clock domain crossing), Synthesis/Static Timing and Power Requirements. Work with CAD and Flow teams to define and improve front-end design methodologies. Develop micro-architecture and design specifications. Implement and verify sophisticated logic designs. Work with designers on STA, physical, power and logical issues. Participate in meetings, discussions, and writing documentation to ensure clear communication and thorough understanding of design requirements and progress. Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec. Optimize power/performance. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.

Experience and/or education must include:

Utilizing System Verilog or Verilog to write RTL for the wireless communication IPs.
Utilizing scripting languages (python, perl, or TCL), including automating the RTL integration flow, synthesis and timing reports, and building hardware modules.
Utilizing CDC, RDC tools, and knowledge of multiple clock domains, multiple reset domains and fix the issues to ensure digital logic is functioning properly.
Utilizing RTL design with complex FSMs, and power saving features.
Utilizing IP integration including clock/reset module design, clock/power gating implementation, fabric/bus-system configuration and design.
Implementing industry low power methodologies including UPF/CPF and lower power check techniques.
Utilizing high speed interface design (source synchronous bus, etc).
Utilizing synthesis tools from Synopsys, Cadence and setting the correct constraints for synthesis, and knowledge of LEC/LEQ tools and ECOs.
Understanding computer architecture and SoC.
Utilizing low power design concepts and implementation, including clock gating, power gating, and DVFS to reduce power consumption.

Preferred Qualifications

N/A