About this role
In this position, you will work closely with design engineering to complete the layout and verification of high-performance mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL and Mentor's Calibre tools, and work with circuit engineers to generate topological layouts to ensure optimal circuit performance.
Responsibilities
- Solving layout design issues and applying proactive intervention
- Proactively work with design engineers to achieve efficient circuit performance
- Design analog & mixed-signal layouts
- Understand device matching techniques
- Understand signal conditioning/protection techniques
- Strong collaboration skills, including written and verbal communication
- Outstanding layout planning and integration skills
- Experience in routing at the block level and chip top-level using assisted/automated tools
Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license. Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role.
Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.