Fpga/asic Engineer

We are looking for a Design Verification Engineer to join our growing verification team. Position Summary As a Design Verification Engineer, you will support the verification of ASIC, SoC, IP, subsystem, and FPGA designs. You will help develop testbenches, create tests, run simulations, debug failures, and contribute to coverage-driven verification under the guidance of senior engineers. This is a hands-on technical role with strong mentorship and learning opportunities. You will gain experience with modern verification methodologies, EDA tools, scripting, simulation debug, and the process of taking complex designs from specification through verification closure. Key Responsibilities Support verification activities for ASIC, SoC, IP, subsystem, and FPGA designs. Develop and maintain verification components using SystemVerilog and, where applicable, UVM. Create and run directed and constrained-random tests to verify design functionality. Assist in developing testbench components such as drivers, monitors, scoreboards, checkers, sequences, and coverage models. Analyze design specifications and work with senior engineers to understand verification requirements. Run simulations and regressions using industry-standard EDA tools. Debug test failures using simulation logs, waveforms, assertions, and guidance from senior engineers. Help collect and analyze functional coverage, code coverage, and regression results. Document verification work, test results, debug findings, and issue resolutions. Collaborate with design, verification, firmware, FPGA, and project teams to resolve issues. Learn and apply best practices in verification methodology, automation, scripting, and reusable testbench development. Participate in design reviews, verification reviews, and technical discussions. Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related technical field & 3 years of experience or more Basic understanding of digital logic, RTL design concepts, and hardware description languages. Exposure to SystemVerilog, Verilog, VHDL, or another hardware description/verification language. Familiarity with simulation, debugging, test development, or verification concepts. Basic scripting or programming experience using languages such as Python, Perl, Tcl, shell scripting, C, or C++. Strong analytical and problem-solving skills. Willingness to learn modern ASIC verification methodologies, including UVM, constrained-random verification, assertions, and coverage-driven verification. Ability to read technical documentation, specifications, and design descriptions. Good written and verbal communication skills. Ability to work effectively in a collaborative engineering environment. Preferred Qualifications Experience with SystemVerilog, Verilog, digital design, computer architecture, embedded systems, or VLSI design. Exposure to UVM or object-oriented programming concepts. Experience writing testbenches for RTL modules. Familiarity with waveform debugging tools and simulation flows. Exposure to industry-standard EDA tools for simulation, debug, or coverage analysis. Experience with FPGA development boards, embedded processors, or hardware/software integration. Familiarity with protocols or interfaces such as AMBA, AXI, APB, AHB, PCIe, Ethernet, DDR, USB, MIPI, SPI, I2C, or UART. Exposure to assertions, functional coverage, code coverage, or regression automation. Experience using version control systems such as Git. Interest in ASIC design services, custom silicon development, or customer-focused engineering environments.
Job Type & Location
This is a Permanent position based out of Saint Paul, MN.
Pay and Benefits
The pay range for this position is $110000.00 - $185000.00/yr. Individual compensation offered for this position within this range will depend on many factors, including qualifications, skills, relevant experience, job knowledge, geographic location, internal equity, and other pertinent job-related factors. 401k health care medical
bonus potential
Job Type & Location
This is a Permanent position based out of Saint Paul, MN.
Application Deadline
This position is anticipated to close on Oct 28, 2026.
Workplace Type
This is a fully remote position. About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.

The company is an equal opportunity employer and will consider all applications without
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sexual orientation, gender identity, genetic information or any characteristic protected
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Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the
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