About this role

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Silicon Manufacturing and Product Engineering (SMPE) team is instrumental in defining and elivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Package Engineer to join the team to support our mission as a key role with advanced packaging technology selection, qualification, and manufacturing. Responsibilities The principal package engineer will be responsible for providing expertise, insight, and support to the Silicon development team through the entire life cycle of the product. In this role, you will be responsible for supporting the design and implementation of new custom Silicon devices, evaluation and recommendation of new packaging technology, Substrate design support, device/package qualification, supplier assessment, manufacturing bring up, and driving quality/reliability in development and production.<ul type="disc"><li style="font-family: verdana, geneva, sans-serif;">Drive optimal silicon packaging solution supporting Azure datacenter product roadmap.</li><li style="font-family: verdana, geneva, sans-serif;">Drive package technology for chiplet architecture with advanced 2.5D/3D packaging.</li><li style="font-family: verdana, geneva, sans-serif;">Drive 2.5D/3D packaging product designs (bridge/interposer/substrate) from definition, development to tapeout</li><li style="font-family: verdana, geneva, sans-serif;">Define, design and develop test vehicles to validate Silicon, Package, System performance.</li><li style="font-family: verdana, geneva, sans-serif;">Drive supplier assessments and manage suppliers through definition, development, qualification and production.</li><li style="font-family: verdana, geneva, sans-serif;">Develop and deliver FMEA (Failure Mode and Effects Analysis) for various technology options.</li><li style="font-family: verdana, geneva, sans-serif;">Define EDA tools requirements for advanced 3DIC packaging designs</li><li style="font-family: verdana, geneva, sans-serif;">Design and develop package and assembly drawings to support the manufacturing.</li><li style="font-family: verdana, geneva, sans-serif;">Lead supplier assessments and manage suppliers through definition, development, qualification and production.</li><li style="font-family: verdana, geneva, sans-serif;">Assess and characterize the reliability of Integrated Circuits (IC) packages.</li><li style="font-family: verdana, geneva, sans-serif;">Design and develop package and assembly drawings to support the manufacturing.</li><li style="font-family: verdana, geneva, sans-serif;">Work closely with silicon and platform architects, motherboard and package designers, thermal architects and engineers, and power and performance engineers.</li><li style="font-family: verdana, geneva, sans-serif;">Drive execution of architecture solutions across product lines or multiple product groups and across teams that account for design trends and future concepts by leveraging cross-functional expertise, industry best practices, and lessons learned from teams working across multiple product lines.</li><li style="font-family: verdana, geneva, sans-serif;">Drive engineering system design decisions that require collaboration between internal and external stakeholders to account for platform-specific technology decisions and develop system models based on current and anticipated feature/design needs and trade-offs.</li></ul> Qualifications Required Qualifications:<ul><li style="font-family:verdana, geneva, sans-serif">Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. </li></ul> Other Requirements:<ul style="list-style-type:disc"><li style="font-family:verdana, geneva, sans-serif">Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: <ul style="list-style-type:disc"><li style="font-family:verdana, geneva, sans-serif">Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. </li></ul></li><li style="font-family:verdana, geneva, sans-serif">This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.</li></ul> Preferred Qualifications:<ul><li style="font-family:verdana, geneva, sans-serif"><div>Doctorate in Electrical Engineering, Physics, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR Master's Degree in Electrical Engineering, Physics, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Physics, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience.</div></li><li style="font-family:verdana, geneva, sans-serif">15+ years of hands-on experience in Semiconductor Package design, development, manufacturing, supplier management or quality management</li><li style="font-family:verdana, geneva, sans-serif">Specific experience with Advanced Semiconductor Package technologies (e.g. BGA/2.5D/3D)</li><li style="font-family:verdana, geneva, sans-serif"><div>Foundation in advanced packaging technologies, manufacturing and supplier management</div></li><li style="font-family:verdana, geneva, sans-serif"><div>Working knowledge in high-speed signaling, layout, electrical, mechanical and thermal co-designs.</div></li><li style="font-family:verdana, geneva, sans-serif"><div>Working knowledge in defining test vehicle strategies that appropriately envelope product design and use conditions, isolate key technical risks, and generate actionable data to support engineering decisions while balancing test coverage, learning objectives, and program timelines.</div></li><li style="font-family:verdana, geneva, sans-serif"><div>Experience in thermo-mechanical FEA, with the ability to translate simulation results into product design requirements, identify and quantify key failure risks, guide design tradeoffs, and develop risk-mitigation and validation strategies.</div></li><li style="font-family:verdana, geneva, sans-serif"><div>Working knowledge in 2D and 3D simulation tools for full package layout extractions for power and signals analysis</div></li><li style="font-family:verdana, geneva, sans-serif"><div>Experience with OSAT, Supplier & Foundry technologies.</div></li><li style="font-family:verdana, geneva, sans-serif"><div>Experience in physical failure analysis</div></li><li style="font-family:verdana, geneva, sans-serif"><div>Experience in subcontract supplier management.</div></li><li style="font-family:verdana, geneva, sans-serif">Record of success in cross-functional team environment</li></ul><div>#AHSI</div>#SCHIE#CSME #SMPE Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: <a href="https://careers.microsoft.com/us/en/us-corporate-pay">https://careers.microsoft.com/us/en/us-corporate-pay</a> This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. <hr> Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about <a href="https://careers.microsoft.com/v2/global/en/accessibility.html">requesting accommodations.</a>