Senior Silicon DFT Micro Architecture Engineer, Google Cloud

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Design for Testing (DFT) micro-architect/design engineer, you will support the systems that are the heart of the world's largest and most powerful computing infrastructure. You will be part of a team that develops from the lowest levels of circuit design to large system design and sees those systems all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our data centers, affecting millions of Google users.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Minimum qualifications:

- Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.

- 8 years of experience in the implementation and validation of DFT technologies.

- Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.

- Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.

- Experience in leading DFT activities throughout an ASIC development flow.

Preferred qualifications:

- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.

- Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for Multi die SoCs).

- Experience in fault modeling.

- Experience in SoC cycles, silicon bringup, and silicon debug activities.

- Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for high-speed I/Os, Analog DFT).

- Develop and drive die-level DFT validation strategy, complete all Test Design Rule Checks (TDRC), and execute design changes to fix TDRC violations to achieve high test quality.

- Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, clock control block, and other DFT IP blocks.

- Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

- Generate and deliver production and debug patterns to the post-silicon engineering team, and run diagnosis for post-silicon support.