Principal R&D Engineer (3DIC)

Job Description and Requirements

You Are

You have 15+ years of experience and are already drawn to hard technical problems: algorithms, data structures, and software that has to be correct, fast, and maintainable. You may not yet have shipped a full EDA product, but you write solid C/C++, you debug with discipline, and you want to learn how production design tools actually get built.

You are curious about how chips are designed and packaged — and you want to grow into that domain by working on real software, not only on theory. At Synopsys, you will contribute to package substrate design automation within 3DIC Compiler, helping enable advanced multi-die systems for AI, high-performance computing, and heterogeneous integration.

What You'll Be Doing

- Implement and extend package substrate design automation capabilities within the 3DIC Compiler platform.
- Write production C/C++ code for features such as HDI substrate auto-routing, design rule checking, power delivery network analysis, and design for manufacturability.
- Build, test, and debug software that runs on large, real-world packaging designs, including multi-die chiplets and heterogeneous integration.
- Work with senior engineers, product teams, and customers to understand design bottlenecks and turn them into well-scoped software changes.
- Participate in design and code reviews; learn how architecture decisions are made across the 3DIC product.
- Grow your skills in algorithms, performance, and software quality under the mentorship of experienced R&D engineers.

The Impact You Will Have

- Contribute features that help customers design next-generation advanced packaging for AI, high-performance computing, and other complex systems.
- Help reduce design cycle time for teams working on HDI substrates, chiplets, and multi-die architectures.
- Own well-defined pieces of auto-routing, power delivery, checking, and manufacturability software — and see them used by leading semiconductor companies.
- Build a foundation in a strategic Synopsys product line at the center of the industry shift toward chiplet-based systems.

What You'll Need

- Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field.
- 15+ years of relevant software or R&D experience.
- Strong C/C++ skills and a solid grasp of data structures, algorithms, and complexity.
- Ability to write, debug, and test production-quality code; coursework, internships, or projects that show this clearly.
- Interest in physical design, EDA, semiconductors, or advanced packaging — prior domain experience is a plus, not a requirement.
- Coursework or project experience in at least one related area is helpful: graph algorithms, computational geometry, CAD/EDA tools, VLSI/physical design, or large-scale C++ software.
- Clear written and verbal communication, and a willingness to learn from design reviews and feedback.

The Team You'll Be Part Of

You will join the advanced packaging design automation team for 3DIC Compiler. The team focuses on package substrate design and the industry shift toward chiplet architectures and heterogeneous integration. You will be mentored by senior and distinguished engineers, contribute to a strategic Synopsys growth area, and see a clear path to greater ownership as you grow.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.