RISC-V Processor Validation & Test Generation Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is looking for a RISC-V Processor Validation & Test Generation Engineer to help develop tools and test programs that validate processor behavior and improve compliance with RISC-V specifications including the RVA23 profile. You’ll help build, refine, and verify automated test-generation tools that exercise processor functionality, uncover bugs, and identify ambiguities or misunderstandings in architectural specifications. A key part of this role is adapting our existing test-generation programs. You’ll replace the generation of machine-mode code with supervisor-mode code, so our tests exercise RISC-V cores the way real operating systems use them. . You’ll work at the intersection of processor architecture, software development, and hardware validation to generate portable, effective tests that help ensure RISC-V implementations behave as expected. This is an opportunity for a hands-on engineer who understands processor privileged modes and enjoys building practical tools that improve the quality of an open hardware ecosystem.

This role is remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

- You have a strong understanding of RISC-V architecture, instruction sets, and execution behaviors across machine, supervisor, and user modes.

- You enjoy writing and debugging programs that test processors, generate test cases, and uncover functional bugs or discrepancies in architectural behavior.

- You’re comfortable reading technical specifications and translating architectural requirements into executable tests.

- You can use your knowledge of the behavioral differences between executing code in machine mode and supervisor mode to modify machine-mode code generators to produce supervisor-mode code.

- You’re a self-directed problem solver who can take ownership of a specialized engineering task and collaborate with hardware architects and software engineers.

What We Need

- Strong knowledge of RISC-V ISA fundamentals, including instruction behavior differences in machine-, supervisor, and user-mode

- Knowledge of the structure of two-stage RISC-V page tables and the ability to generate them

- Experience writing low-level software, processor tests, validation programs, or test-generation tools using C/C++, assembly, Python, or similar languages.

- Ability to read and interpret processor architecture specifications and translate them into reliable, executable test cases.

- Strong debugging and code-analysis skills, with the ability to modify existing code-generation programs to generate supervisor-mode code that creates page tables and schedules tests

- Ability to work independently on a focused technical project, investigate unfamiliar code, and deliver maintainable, well-documented solutions.

What You Will Learn

- How RISC-V processor test-generation tools work and how they are used to validate architectural compliance.

- How to develop tests that distinguish architectural requirements from implementation-specific behavior.

- How machine-mode code and processor execution environments affect test portability and validation strategy.

- How automated testing can uncover processor bugs, specification ambiguities, and inconsistencies across implementations.

- How Tenstorrent contributes to the broader RISC-V ecosystem through processor validation, test development, and certification support.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.