FPGA IP Design Engineer - Intern

Job Details:

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Job Description:

Altera’s IP Design and Flows (IPDF) team develops end-to-end solutions that give customers efficient access to the capabilities of Altera FPGA devices. We deliver highly configurable intellectual property (IP) cores that are fully integrated with Altera’s CAD software, Quartus Prime.

Our team builds IP cores and user flows for advanced chip-to-chip interfaces, including high-speed ADC/DAC tiles, leading-edge transceiver interfaces (Ethernet, PCIe, and other protocols), and external memory interfaces such as DDR5, LPDDR5, and High Bandwidth Memory (HBM) over a high-speed Network-on-Chip (NoC).

These IP cores and flows provide configurable access to high-speed, high-bandwidth memory, chip-to-chip connectivity, and transceiver protocols. Because most customer systems require packet processing, storage, or buffering, this work sits at the center of modern electronic system design. Rising device speeds and growing architectural complexity create challenging problems that demand system-level expertise across silicon, software, IP, and customer applications.

As an IP Design Engineer - Intern, you will collaborate with a multidisciplinary engineering team to develop and verify IP cores and associated design flows. Your work will span advanced architecture definition, RTL implementation, verification, design examples, simulation models, and technical documentation.

Responsibilities

Your responsibilities may include, but are not limited to:

- Architecture and design based on the latest protocol specifications for memory, chip-to-chip, or transceiver interfaces RTL development
- Design entry flows for user configuration
- Device support and CAD tool integration
- Verification (e.g. verification IP, methodologies, frameworks, bus functional models, regression tests)
- Hardware power-on and debug
- New product release and rollout support
- Customer technical support

Behavioral traits

- Strong communication, initiative, innovation, and teamwork
- Motivation to learn and adapt in a fast-changing technology environment
- Excellent problem-solving skills and attention to detail
- Accountability, integrity, and a results-oriented mindset
- Collaborative working style, strong influencing skills, and willingness to work across global teams

Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position’s location, as well as the candidate’s experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success.​

Estimated Salary Range: $95K– $100K CAD​

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We use artificial intelligence to screen, assess, or select applicants for the position.​ This posting is for an existing vacancy.​ Canadian work experience is not required for this role. Applicants must be eligible for any required Canada export authorizations.

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Qualifications:

Minimum Qualifications:

- The candidate must be pursuing a Bachelor’s Degree in Computer Engineering, Engineering Science, Computer Science, Math, Electrical Engineering or equivalent
- 3+ months of experience in Digital logic hardware (e.g. SystemVerilog, Verilog and/or VHDL) design or verification
- 3+ months of experience in Software programming or scripting (e.g. C/C++ and/or Python)

Preferred Qualifications:

- Familiarity with FPGA development flows and tools such as Quartus
- Experience working on hardware-software co-design or embedded systems projects
- Strong analytical and problem-solving skills

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## Job Type:
Student / Intern (Fixed Term)

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## Shift:
Shift 1 (Canada)

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## Primary Location:
Toronto, Ontario, Canada

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Additional Locations:

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## Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.