Principal Product Engineer

MicrosoftRedmond, WashingtonOn-siteFull-timePrincipal, 12–15+ yearsListed 2 hours ago

Apply now

About this role

<b>Overview</b><br><p><span style="font-family: verdana, geneva, sans-serif; color: black;">Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (<em>SCHIE</em>) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.</span></p><p><span style="font-family: verdana, geneva, sans-serif; color: black;">The Compute Silicon &amp; Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.</span></p><p><span style="font-family: verdana, geneva, sans-serif; color: black;">As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the <strong>Silicon Manufacturing and Product Engineering</strong><strong> (SMPE) </strong>team is instrumental in defining and elivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.</span></p><p><span style="font-family: verdana, geneva, sans-serif; color: black;">We are looking for a <strong>Principal Product Engineer</strong> to join the team.</span></p><p> </p><br><br><b>Responsibilities</b><br><p><span style="font-family: verdana, geneva, sans-serif; color: black;">The position will have responsibility for product/test engineering for new product development and manufacturing.</span></p><ul type="disc"><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;">The position requires someone with experience in semiconductor IC development, IC manufacturing, fabrication, testing, and packaging.</span></li><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;">Drive pre-Si readiness for power, performance, Thermal and Power delivery (LDOs, Integrated VRs) related tests and features for successful bring up during power on. Drive Power and Performance tuning during post-Si phase in partnership with platform teams.</span></li><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;">Drive ATE test program implementation to optimize for SOC power/TDP. Work closely with platform/system engineers to drive necessary correlation work to enable such optimizations.</span></li><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;">Drive product manufacturing fuse requirements and end to end data flow for fusing across various test sockets.</span></li><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;">Successful candidates should have strong project leadership skills to manage external vendors, drive cross functional teams and drive sub-projects as part of larger development programs.</span></li><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;">They should also have excellent knowledge of ATE test program development including test method development, test bring-up, characterization, debug, and yield analysis.</span></li><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;">The candidate should also have knowledge of DFT, silicon fabrication process, product Q&amp;R, and basic transistor theory.</span></li><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;">The candidate would benefit from a background in various product market areas such as high-performance computing, AI, GPUs, CPUs.</span></li><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;">Overall product engineering role taking product from definition to launch.</span></li><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;"><strong>Adaptability</strong> (responds, explores, constructive attitude) </span></li><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;"><strong>Growth Mindset</strong> (It starts with a belief that everyone can grow and develop)       </span></li><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;"><strong>Customer Focus</strong> (anticipates needs and proactively meets expectations)   </span></li><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;"><strong>Drive for results</strong> (actively pursues outcome, delivers on commitments)     </span></li><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;"><strong>Influence for impact</strong> (communicates, networks, persuades, influences)    </span></li><li style="font-family: verdana, geneva, sans-serif; color: black;"><span style="font-family: verdana, geneva, sans-serif; color: black;"><strong>Judgement</strong> (scope problem, builds &amp; applies knowledge) </span></li></ul><br><br><b>Qualifications</b><br><p><span style="font-family: verdana, geneva, sans-serif;"><strong><u>Required Qualifications:</u></strong></span></p><ul><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.</span></li></ul><p style="font-family: verdana, geneva, sans-serif;color: black;"> </p><p><span style="text-decoration: underline;"><span style="font-family: verdana, geneva, sans-serif;"><strong>Other Requirements:</strong></span></span></p><ul style="list-style-type: disc;"><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: </span><ul style="list-style-type: disc;"><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.  </span></li></ul></li><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.</span></li></ul><p> </p><p><span style="font-family: verdana, geneva, sans-serif;"><strong><u>Preferred Qualifications</u></strong></span></p><ul type="disc"><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">8+ years of experience in Product development and manufacturing in large scale and/or high performance (i.e., AI, machine leaning, neural nets, CPU’s) and/or high power SoCs/chips.</span></li><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">8+ years of experience in Developing Integrated Circuits (pre-silicon, first silicon bring-up, new product introduction).</span></li><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">5+ years of experience in product and test engineering, ATE test program development and debug (Advantest V93K experience is a plus)</span></li><li style="font-family: verdana, geneva, sans-serif;">Excellent presentation and communication skills, with the ability to influence, engage, and communicate effectively with stakeholders at all levels.</li><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">Experience in:</span></li><ul type="circle"><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">Leading cross functional teams and understanding program/project management.</span></li><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">Managing supply chain, vendors / partners, and Integrated Circuit production.</span></li><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">Experience in system/customer requirements gathering and interfacing.</span></li><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">Si configuration (SKU) management and internal supplier/customer interfacing</span></li><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">End-to-end product development flow and driving sample delivery milestones across the life cycle (Quality &amp; Quantity)</span></li></ul><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">Knowledgeable in power / performance modelling for ATE binning optimization in both pre- and post-silicon phases of the program. In-depth understanding of ATE test program power/performance binning implementation including required characterization data collection.</span></li><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">Knowledgeable in yield recovery definition (redundancy and repair for logic, array, analog) and their implementation (test programs, test content, SKU). Drive implementation partnering with cross-functional teams.</span></li><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">System and Platform validation background is a plus. Experience working across various platforms (ATE/RVP/Customer boards) for product validation and characterization.</span></li><li style="font-family: verdana, geneva, sans-serif;"><span style="font-family: verdana, geneva, sans-serif;">Experience with failure analysis, qualification, and yield analysis</span></li></ul><p style="font-family: verdana, geneva, sans-serif; color: black;"> </p><p><span style="font-family: verdana, geneva, sans-serif;"><strong>#SCHIE </strong></span></p><p><span style="font-family: verdana, geneva, sans-serif;"><strong>#CSME </strong></span></p><p><span style="font-family: verdana, geneva, sans-serif;"><strong>#SMPE</strong></span></p> <br><br><p>Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. </p><p></p> <p>Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:<br><a href="https://careers.microsoft.com/us/en/us-corporate-pay">https://careers.microsoft.com/us/en/us-corporate-pay</a></p><br><p>This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.</p><br><hr><br><p>Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about <a href="https://careers.microsoft.com/v2/global/en/accessibility.html"><b><u>requesting accommodations.</u></b></a></p>