Senior Firmware Engineer

MicrosoftMountain View, CaliforniaHybrid, On-siteFull-timeSenior, 5–8 yearsListed 6 days ago

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About this role

<b>Overview</b><br><p style="margin-right: 11.25pt; line-height: 11.8pt; margin-left: 0.0in; font-size: 12.0pt; font-family: 'Times New Roman', serif;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="color: #242424;">Microsoft Silicon and Cloud Hardware Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Skype, OneDrive and the Microsoft Azure platform globally </span><span style="color: black;">with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our </span><span style="color: #242424;">focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high energy engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and HW infrastructure on time, in high volume with high quality and lowest cost is of paramount importance.</span></span></p><p style="margin: 0.0in 0.0in 8.0pt; font-size: 11.0pt; font-family: Calibri, sans-serif; line-height: 107%;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span class="contentpasted0"><span style="color: black;">The FW/</span><span style="color: black;">SW</span></span><span class="contentpasted0"><span style="color: black;"> CoE </span><span style="color: black;">team</span></span><span style="color: black;"> is responsible for HW/FW for Azure Infrastructure. We are working on the next generation HW/FW for server, silicon and rack infrastructure with a focus on innovation in firmware technology to secure Azure infrastructure for Microsoft and their customers.</span></span></p><p style="margin: 0.0in 0.0in 8.0pt; font-size: 11.0pt; font-family: Calibri, sans-serif; line-height: 107%;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="color: black;">We are looking for a highly motivated </span><span style="color: black;">background in Silicon design, firmware development,  validation, and debug to work on lighting up the various features and technologies as each team produces their part. You must have experience with SoC Architecture and Design, Bring-Up of new silicon and platform, root causing issues at the intersection of multiple subsystems across firmware and hardware. </span></span></p><p style="margin: 0.0in 0.0in 8.0pt; font-size: 11.0pt; font-family: Calibri, sans-serif; line-height: 107%;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="color: #242424;">#Azure  #SCHIE   #S</span><span style="line-height: 107%; color: #242424;">CHIEFWCOE</span><span style="color: #242424;"> </span></span></p><br><br><b>Responsibilities</b><br><ul><li style="line-height: normal; font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Design and implement low-level SoC firmware and silicon firmware libraries. </span></li><li style="line-height: normal; font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Own firmware for one or more IPs/subsystems from architecture through production. </span></li><li style="line-height: normal; font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Work with silicon architects to define firmware/HW interfaces and initialization flows. </span></li><li style="line-height: normal; font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Develop reusable, modular firmware APIs and frameworks. </span></li><li style="line-height: normal; font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Develop and debug boot, initialization, reset, error handling and recovery flows. </span></li><li style="line-height: normal; font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Participate in pre-silicon validation and first-silicon bring-up. </span></li><li style="line-height: normal; font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Perform system-level debugging across firmware, hardware and software boundaries. </span></li><li style="line-height: normal; font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Analyze complex failures using logs, telemetry, register state and hardware debug tools. </span></li><li style="line-height: normal; font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Work closely with architecture, RTL/DV, validation, security, platform firmware and driver teams. </span></li><li style="line-height: normal; font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Drive issues independently from reproduction through RCA and resolution. </span></li><li style="line-height: normal; font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Improve firmware quality through unit tests, validation automation and reusable test infrastructure. </span></li><li style="line-height: normal; font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Mentor engineers and influence technical design within the feature/subsystem area.</span></li></ul><br><br><b>Qualifications</b><br><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><strong>Required Qualifications:</strong></span></p><ul style="list-style-type: disc;"><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience </span><ul style="list-style-type: disc;"><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">OR equivalent experience. </span></li></ul></li></ul><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><strong>Other Requirements:</strong></span></p><ul style="list-style-type: disc;"><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:</span><ul style="list-style-type: disc;"><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.</span></li></ul></li></ul><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><strong>Preferred Qualifications:</strong></span></p><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">7–10 years of industry experience in firmware design, development and productization, preferably including several years on server-class platforms.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Strong understanding of SoC architecture, particularly server-class SoCs.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Experience implementing microarchitecture (Arm and x86), firmware design and design verification.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Deep expertise in one or more of these domains: management and user cores, security IPs and flows, boot sequences, and IP-level silicon firmware library development.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Strong experience in pre-silicon validation using simulation and emulation platforms such as FPGA, ZeBu and Palladium.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Hands-on experience with silicon bring-up and post-silicon validation.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Strong SoC debug expertise, including required hands-on experience with tools such as JTAG, Arm Development Studio (Arm DS) and Lauterbach TRACE32.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Experience in ATE (automated test equipment) environments and initial wafer bring-up.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Knowledge of platform and security firmware, such as Arm TrustZone.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Good understanding of operating system driver development for Linux and Windows.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Experience leading a small team of engineers.</span></li></ul> <br><br><p>Firmware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year. </p><p></p> <p>Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:<br><a href="https://careers.microsoft.com/us/en/us-corporate-pay">https://careers.microsoft.com/us/en/us-corporate-pay</a></p><br><p>This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.</p><br><hr><br><p>Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about <a href="https://careers.microsoft.com/v2/global/en/accessibility.html"><b><u>requesting accommodations.</u></b></a></p>