About this role
Description
Annapurna Labs, an Amazon company, designs and delivers high-end, custom silicon that sits at the very heart of AWS. Our devices don't just support the cloud — they actively define it. From Trainium, the purpose-built machine learning accelerator driving the next wave of AI innovation, to Graviton, the Arm-based server processor redefining price-performance for compute workloads, to Nitro, the advanced network and cloud management controller that powers every AWS instance — Annapurna's products consistently set the standard for the entire industry.
This is an exciting opportunity to join Amazon in developing the next generation of cloud products, in a highly collaborative, team-oriented environment.
We are hiring a Senior SerDes Characterization Engineer to join the Signal Integrity and Packaging (SiP) group at Amazon's Annapurna Labs. This is a hands-on technical position for an experienced lab engineer who will lead characterization efforts for high-speed serial protocols in advanced semiconductor platforms.
You will design and execute comprehensive lab characterization campaigns, troubleshoot complex signal integrity issues, and drive data-driven optimization across PCIe, Ethernet, and other industry-standard serial interfaces. This role requires deep technical expertise, strong hardware debugging skills, and the ability to work independently while collaborating with cross-functional design and validation teams.
Key job responsibilities
- Lead SerDes characterization campaigns for PCIe, Ethernet, UCIe, and other serial protocols on advanced silicon and package platforms
- Design comprehensive test plans covering eye diagrams, bathtubs, jitter analysis and protocol compliance
- Operate and troubleshoot industry-standard lab equipment: oscilloscopes, spectrum analyzers and VNAs
- Analyze complex waveform and signal data; identify root causes of performance issues and signal integrity problems
- Collaborate with design teams to validate silicon behavior, debug hardware anomalies, and optimize link margins
- Develop characterization scripts and measurement techniques to improve efficiency and repeatability
- Mentor junior engineers and contribute to hardware design reviews from a characterization perspective
- Document findings and present technical results to stakeholders and leadership
A day in the life
As a Senior SerDes Characterization Engineer, you will own the lab characterization and validation of high-speed serial interfaces — from test plan definition and bench setup through silicon and board bring-up, link debug. You will work hands-on with oscilloscopes, VNAs and other test equipment.
You will collaborate closely with cross-functional teams, including board design, packaging, ASIC, and firmware teams, to isolate link failures to their true source and drive them to closure. In addition, you will serve as the technical focal point for characterization on your projects — defining measurement methodology, making the judgement calls on what a marginal eye means, and setting the standard for how link margin is proven before silicon ships.
Basic Qualifications
- 10+ years of hands-on lab characterization experience with SerDes protocols (PCIe, Ethernet, or equivalent high-speed serial interfaces)
- Expert-level proficiency with oscilloscopes, spectrum analyzers and VNAs
- Deep understanding of signal integrity, jitter, eye diagrams, and link budget analysis
- Strong troubleshooting and problem-solving skills in hardware bring-up and platform validation
- Experience with protocol compliance testing and standards (PCIe, Ethernet, USB, or similar)
- Bachelor’s degree in electrical engineering or equivalent field with substantial lab experience
Preferred Qualifications
- Experience characterizing multiple SerDes protocols (PCIe, Ethernet, UCIe)
- Familiarity with high-speed package design, signal routing, and layout considerations
- Experience with automated measurement systems and scripting
- Background in silicon bring-up or hardware platform validation
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