Solution Architect, FPGA/SoC - AECG

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THE TEAM:

The AECG - Embedded Team builds and optimizes platforms for embedded and commercial applications, working across silicon, firmware, and software to deliver reliable, high‑performance solutions at scale

THE ROLE:

The Solution Architect is part of AMD's Adaptive and Embedded Computing Group (AECG, formerly Xilinx) Product, Software and Solutions team  located in San Jose CA, Longmont CO, Ottawa Ont. and Vancouver BC. The Solutions Planning Team is looking for an experienced leader to scale the teams’ ability to deliver customer focused solutions for the next generation AECG Platforms.

KEY RESPONSIBILITIES:

- Partner with s ilicon planning and architecture teams help define features for next generation FPGA and SOC product families.

- Collaborate with market segment architects and business leads to create customer focused solutions to address the complex needs of customers in Aerospace and Defense, Automotive, Wired and Wireless Networks , Test and Measurement , Medical, Industrial and Vision markets.

- Work closely with Vivado and Vit i s Tools , IP, system software, and boards engineering and marketing team s to define and drive deliverables as part of the overall solution plan for next generation s ilicon devices.

- Work with product marketing and engineering teams to prioritize and align solution deliverables during release planning processes.

- Present solution progress updates to executive and deliver solution, silicon, and customer application presentations to internal marketing and engineering teams.

PREFERRED REQUIREMENTS:

- Experienced System Architect, Application Engineer , or T echnical M arketing Engineer /Manager with in-depth digital system experience .

- Ability to understand a broad set of applications from traditional FPGA centric applications such as wired communications to emerging applications in Artificial I ntelligence, Machine learning, Autonomous Driving, and advanced DSP processing.

- Have experience with AECG (Xilinx) FPGA products and exposure to Vivado and Vitis design tools.

- Have experience with interface protocols such as PCIe, (LP) DDR , MIPI, DisplayPort, HDMI, SDI, Ethernet, and JesD .

- Ability to break down large complex problems into manageable deliverables and be able to manage and prioritize requirements from many stakeholders.

- Thrive in a fast-paced environment at the forefront of new technology and invention .

- Beneficial to have prior design experience with ASIC’s, FPGA’s, RF design, or embedded software.

- B enefi cial to have Project Management experience , excellent organizational skills, and a process-oriented mindset .

ACADEMIC CREDENTIALS:

- BS/MS in CS/ CE/ EE with significant relevant industry experience

LOCATION:

San Jose, CA preferred.

This role is not eligible for visa sponsorship.

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Benefits offered are described:  AMD benefits at a glance .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.