Engineer - Physical design

Job Overview:

We are looking for a Physical Engineer specialized in building with 1–2 years of relevant experience to join our SoC implementation team. You will contribute to next-generation SoC projects, working across the synthesis-to-GDSII flow.

This role offers hands-on experience in physical implementation, timing analysis, debugging and power, performance and area (PPA) optimization. You will collaborate with design , verification, DFT and physical IP teams, using scripting and AI-assisted workflows to improve engineering efficiency.

Responsibilities:

- Complete and support RTL synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and GDSII generation with mentorship from senior engineers.

- Analyze and improve PPA through synthesis and physical implementation.

- Conduct static timing analysis with Synopsys PrimeTime, troubleshoot setup and hold violations, and assist in achieving timing closure across operating modes and corners.

- Review timing constraints, tool reports and implementation results to identify issues, investigate root causes and propose fixes.

- Assist with physical verification and final approval processes, including DRC, LVS, signal integrity, and EM/IR analysis.

- Develop Python and Tcl scripts to automate implementation tasks, analyze reports and track quality.

- Use approved AI tools and agents to assist with scripting, report analysis and debugging, while independently validating their outputs.

- Document results, communicate technical findings and collaborate with teams to resolve implementation issues.

Necessary Skills and Experience:

- Bachelors or Masters degree in Electronics, Electrical Engineering, Microelectronics, VLSI or a related field.

- 1–2 years of relevant experience in ASIC/SoC physical design or implementation.

- Familiarity with the RTL-to-GDSII process, encompassing synthesis, floorplanning, placement, CTS, routing, and timing closure.

- Understanding of physical designfundamentals, including utilization, congestion, clock skew, latency, buffering and cell sizing.

- Hands-on experience with PrimeTime and at least one synthesis or physical implementation tools such as Fusion Compiler, Genus or Innovus.

- Knowledge of static timing analysis, including setup/hold checks, clock definitions, timing exceptions and multi-mode, multi-corner analysis.

- Ability to read Verilog RTL and gate-level netlists and trace timing paths to investigate implementation issues.

- Practical programming skills in Python, familiarity with Tcl, and confidence working in a Linux environment.

- Strong analytical and debugging skills, clear communication and a willingness to learn and take ownership of assigned tasks.

Preferred Skills and Experience:

- Exposure to advanced-node, hierarchical implementation or large SoC integration.

- Familiarity with low-power concepts, UPF, multiple voltage domains, power gating and level shifters.

- Exposure to on-chip variation, timing derates, crosstalk and signal integrity.

- Basic knowledge of power distribution networks, EM/IR analysis, IO placement, and bump-planning considerations.

- Familiarity with DFT requirements and physical verification flows.

- Experience using AI coding assistants or agents for engineering automation, including effective task definition, output validation and responsible handling of proprietary build data.

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Use of AI in Your Application

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Recruitment Adjustments and Accommodations

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [email protected] . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.