ASIC Verification Engineer, Networking

Meta is hiring an ASIC Design Verification, Networking Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.

As a Design Verification Engineer, you will be part of a team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test planning, UVM-based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

Responsibilities

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
Develop functional tests based on the verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Collaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams towards ensuring design quality meets defined verification and coverage goals
Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools, and technologies from the industry

Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience
8+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies and/or C/C++ based verification
Experience in one or more of the following areas, along with functional verification - Ethernet, 400G MAC, NIC, RDMA, PSP, RoCE (RDMA over Converged Ethernet), congestion control, etc
Experience in architecting and implementing design verification infrastructure, and in executing the full verification cycle
Proficiency in scripting languages such as Python, Perl, or TCL to build tools and workflows for verification environments
Experience in debugging and resolving complex verification challenges in IP or SoC designs
Experience collaborating with cross-functional teams such as design, emulation, and silicon validation to drive verification milestones Experience with IP or integration verification of high-speed interfaces like Ethernet, PCIe, DDR, HBM
Experience working across and building relationships with cross-functional design, model, and emulation teams
Experience with the verification of ARM/RISC-V based sub-systems or SoCs
Experience with the development of fully automated flows and scripts for data exploration, analysis, and performance verification