About this role

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Silicon Logic Design team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior Logic Design Engineer to join the team designing RTL for a high-performance PCIe Subsystem supporting Azure Cobalt. #SCHIE #CSME Responsibilities The candidate for this position will be expected and able to complete the following responsibilities:<ul style="margin-bottom:0.0in;margin-top:0.0px"><li style="margin:0.0in 0.0in 0.0in 24.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Build a PCIe subsystem composed of multiple IP </li><li style="margin:0.0in 0.0in 0.0in 24.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Collaborate with architecture and IP providers to ensure the subsystem meets SOC requirements.</li><li style="margin:0.0in 0.0in 0.0in 24.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Grow your micro-architectural knowledge of your own blocks as well as other blocks in the SoC. </li><li style="margin:0.0in 0.0in 0.0in 24.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Assess and then refine the implementation for area, power and performance. </li><li style="margin:0.0in 0.0in 0.0in 24.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Perform design quality checks such as Synthesis, Lint, CDC, RDC, Low Power Intent, Logic Equivalence. </li><li style="margin:0.0in 0.0in 0.0in 24.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Understand Dataflow and Clocking requirements and drive solutions for timing critical paths. </li><li style="margin:0.0in 0.0in 0.0in 24.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Automate tasks using scripting for efficiency. </li><li style="margin:0.0in 0.0in 0.0in 24.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Delight your customers who receive your deliverable by providing high-quality functional block on schedule and with professional integrity. </li><li style="margin:0.0in 0.0in 0.0in 24.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Collaborate with highly energetic cross functional team members with respect and with One Microsoft mentality to establish synergies. </li><li style="margin:0.0in 0.0in 8.0pt 24.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Challenge the status quo with a growth mindset.</li></ul> Qualifications Required Qualifications:<ul><li style="color:black;line-height:normal;background-color:white;font-size:11.0pt;font-family:Calibri, sans-serif">Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience <ul><li style="color:black;line-height:normal;background-color:white;font-size:11.0pt;font-family:Calibri, sans-serif">OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience </li><li style="color:black;line-height:normal;background-color:white;font-size:11.0pt;font-family:Calibri, sans-serif">OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience </li><li style="color:black;line-height:normal;background-color:white;font-size:11.0pt;font-family:Calibri, sans-serif">OR equivalent experience. </li></ul></li></ul>Other Requirements:<ul style="margin-bottom:0.0in;margin-top:0.0px"><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: <ul style="margin-bottom:0.0in;margin-top:0.0px"><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. </li></ul></li><li style="margin:0.0in 0.0in 8.0pt 0.0px;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif">This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.</li></ul><div> </div>Preferred Qualifications:<ul style="margin-bottom:0.0in;margin-top:0.0px"><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Experience with high speed PCIe designs and protocols</li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Experience with Industry standard interface protocols such as AXI, APB, etc. </li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Experience with ARM Fabric IPs</li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Experience with IPXACT</li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Understanding of Computer Architecture fundamentals</li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Ability to write scripts using Python, Tcl, Perl etc. </li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus</li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Proficiency with UPF (Low power intent). </li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Proficiency in clock crossing techniques </li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.</li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Applied understanding of low power design principles. </li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Understanding design closure challenges with power and clock domain crossings.</li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Experience writing timing constraints, exceptions, and clock constraints; good understanding in SDC commands and TCL constraints</li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Organized and detail-oriented</li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">Good verbal and written communication skills.</li></ul> <div> </div> Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: <a href="https://careers.microsoft.com/us/en/us-corporate-pay">https://careers.microsoft.com/us/en/us-corporate-pay</a> This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. <hr> Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about <a href="https://careers.microsoft.com/v2/global/en/accessibility.html">requesting accommodations.</a>