DFT Engineer

Job Requirements

Who We Are:

Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you. The achievers and courageous challenge-crushers we seek, have the following characteristics and skills

What You Will Do:

We are seeking a highly experienced Design for Test (DFT) Engineer to contribute to the development of complex SoC/ASIC designs. This role will focus on DFT planning, integration, testing methodologies, and continuous improvement of DFT flows across chip-level and block level implementations.

Key Responsibilities:

• Develop and implement top-level and block-level DFT plans and integrations

• Utilize Tessent tool flow extensively across DFT processes

• Perform ATPG generation and support ATE interface integration

• Support ATE bring-up and conduct silicon failure analysis and debugging

• Analyze and reduce test time while maintaining high quality standards

• Execute synthesis, STA, and simulation for DFT modes

• Perform formal verification and ensure design correctness

• Implement and manage multi-power domain DFT strategies

• Troubleshoot complex DFT issues and drive continuous DFT flow improvements

What You Will Bring:

• Bachelor’s degree with 8+ years of experience OR Master’s degree with 9+ years of experience

• Extensive hands-on experience in DFT for ASIC/SoC designs

• Strong expertise in chip-level DFT planning and integration

• Deep knowledge of LBIST (at-speed scan), ATPG, MBIST, and JTAG

• Experience with test time reduction methodologies

• Solid understanding of low power DFT and fault modeling (stuck-at, transition, path delay, IDDQ, etc.)

• Experience with silicon failure analysis and debugging

• Strong knowledge of static timing analysis (STA)

• Experience with DFT simulations including timing considerations

• Familiarity with ASIC/SoC design flows, including low power and multi-power domain designs

• Experience working with Mentor DFT tools or similar EDA tools

Pay Range: $160000 - $220000

Compensation decisions are made based on factors including experience, skills, education, and other job-related factors, in accordance with our internal pay structure. We also offer a comprehensive benefits package, including health insurance, paid time off, and retirement plan.

Work Requirements:

This role is considered an on-site position located in San Jose / San Diego / Irvine , CA

- You must be able to commute to and from the location with your own transportation arrangements to meet the required working hours.

Benefits

Full-time (Regular)

• 401(k)

• 401(k) matching

• Dental insurance

• Health insurance

• Life insurance

• Paid time off

• Referral program

• Vision insurance

• Short/Long Term Disability