About this role
Job Description and Requirements
We are seeking an experienced DDR PHY design manager to lead our high-performance MemPHY team. This senior role will oversee all aspects of digital related PHY design for cutting-edge PHY architectures targeting various process nodes.
Responsibilities:
- Manage and mentor a team of 3-6 senior designers focused on high-speed MemPHY IP across multiple projects
- Collaborate with cross-functional teams (verification, controller, physical design, release, PEM, etc.) to develop IP and documentation efforts
- Partner with AE and PEM teams to enable good user experience for various IP integration and silicon bring-up for global customers
- Participate in digital IP design and methodology improvements and adoption of latest EDA tools/flows
Requirements:
- Bachelor's degree in electrical engineering; advanced degree preferred
-10+ years of experience in mixed-signal IC design with a strong background in PHY architectures
- 3+ years of people management experience leading high-performance design team
- Proven expertise in high-speed PHY design, architectures, circuits, and timing implementation
- Good understanding of HBM, DDR, HBI/UCIe protocols
- Good people leadership abilities and project management skills with the ability to manage multiple priorities
- Excellent communication in both Mandarin and English
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.