About this role
Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.
Responsibilities:
- Responsible for the hardware architecture design, architectural performance analysis, and optimization of key NPU modules in next-generation chips.
- Responsible for performance modeling and analysis of emerging deep learning algorithms on chip systems; deliver inference performance for different models and assist in defining chip specifications such as compute throughput, bandwidth, and memory.
- Responsible for architecture optimization targeting real-world application scenarios, achieving hardware-software co-optimization design.
- Responsible for authoring architecture specification documents for key chip modules, and guiding the design implementation, optimization, and verification of the microarchitecture.