About this role
- Job Title : Design Engineer
- Client: Arrow Electronics
- Work Location: Bay Area ,CA, onsite
- Visa : All visa, except H1B transfer
- C2C engagements are allowed.
Need Design Engineer with very strong experience Timing Constraints Writing. (this must reflect in resume)
RTL to Physical Design (RTL2PD) stage experience
RTL2PD Design Engineer(ASIC)
MUST HAVE : RTL Synthesis, Constraint writing, validation, Static timing Analysis
What candidate will Be Doing:
- RTL Synthesis, Constraint writing, validation, Static timing Analysis
- Writing Scripts/Modiying scripts for RTL synthesis, SDC creation, STA
- Debug synthesis issues and STA
- Generate clean netlist.
What we are looking for:
- Experience: 8–12 years of hands-on RTL Synthesis
- EDA exposure: Design compiler, PrimeTime, Tempus, Genus,
- Multi-Node Design: Experience working with 16nm, 7nm… etc nodes.