About this role

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Verification & Validation team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for an experienced engineer with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Design Verification Engineer to join the team. #SCHIE #CSME Responsibilities The candidate for this position will be expected and able to complete the following responsibilities:<ul style="margin-top: 0in; margin-bottom: 0in;"><li style="margin: 0in 0in 0in 24px; font-size: 12pt; font-family: 'Times New Roman', serif;">Own or lead functional or performance verification of one or more aspects of Fabric Top subsystem integration, including coherency, traffic flows to and from memory and PCIe/CXL endpoints, and end-to-end interconnect functionality.</li><li style="margin: 0in 0in 0in 24px; font-size: 12pt; font-family: 'Times New Roman', serif;">Partner with architecture, design, and verification teams to define verification strategies, test plans, and signoff criteria. </li><li style="margin: 0in 0in 0in 24px; line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Develop and enhance UVM and/or Formal verification environments, performance measurement tools, automation infrastructure, and reusable collateral. </li><li style="margin: 0in 0in 0in 24px; line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Drive bug discovery and root-cause analysis through simulation, formal analysis, assertions, coverage, and debug. </li><li style="margin: 0in 0in 0in 24px; line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Improve verification productivity through automation, methodologies, and AI-driven solutions. </li><li style="margin: 0in 0in 0in 24px; line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Coach and mentor engineers in verification methodologies and best practices.</li><li style="margin: 0in 0in 0in 24px; line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion</li></ul> Qualifications Required Qualifications:<ul style="margin-bottom:0.0in;margin-top:0.0px"><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:verdana, geneva, sans-serif">Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience <ul style="margin-bottom:0.0in;margin-top:0.0px"><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:verdana, geneva, sans-serif">OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience </li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:verdana, geneva, sans-serif">OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience </li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:verdana, geneva, sans-serif">OR equivalent experience. </li></ul></li></ul> Other Requirements<ul style="margin-bottom:0.0in;margin-top:0.0px"><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:verdana, geneva, sans-serif">Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. </li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif">This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.</li></ul> Preferred Qualifications:<ul style="margin-bottom:0.0in;margin-top:0.0px"><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:verdana, geneva, sans-serif">Experience of one or more of the following: fabric interconnects, coherency, CHI, AMBA, PCIe, CXL, protocol bridges, or memory subsystems. </li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:verdana, geneva, sans-serif">Experience in architecting and developing UVM verification environments, assertions, checkers, and coverage models. </li><li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Experience driving IP verification for multiple product cycles from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff</li><li style="margin:0.0in 0.0in 0.0in 0.0px;font-size:12.0pt;font-family:verdana, geneva, sans-serif">Demonstrated hands-on technical leadership such as creating bottom’s up schedules, coordinating work across a team, driving verification closure, or solving cross-team technical problems</li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:verdana, geneva, sans-serif">Experience with Formal Verification and assertion-based verification methodologies. </li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:verdana, geneva, sans-serif">Proficiency with Python or similar scripting languages for automation and data analysis. </li><li style="margin:0.0in 0.0in 0.0in 0.0px;line-height:normal;font-size:11.0pt;font-family:verdana, geneva, sans-serif">Experience applying AI-assisted tools to engineering and verification workflows.</li></ul> Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: <a href="https://careers.microsoft.com/us/en/us-corporate-pay">https://careers.microsoft.com/us/en/us-corporate-pay</a> This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. <hr> Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about <a href="https://careers.microsoft.com/v2/global/en/accessibility.html">requesting accommodations.</a>