About this role

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Artificial Intelligence System on Chip (AISoC) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Principal Design Engineer to join the team. Responsibilities <ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Deliver premium-quality silicon designs that push the boundaries of what is possible.</li><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Develop cutting-edge custom Intellectual Property (IP) and System-on-Chip (SoC) designs.</li><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Build solutions capable of complex, high-performance functions with exceptional efficiency.</li><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Bring passion, drive, and intellectual curiosity to solving challenging Computer and Electrical Engineering problems.</li><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Serve as an integral member of the digital logic design team developing AI components, with a focus on microarchitecture-based functions and features.</li><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Own logic design and Register Transfer Level (RTL) implementation for high-performance digital IP.</li><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Drive design quality across Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power, and related design requirements.</li><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Support timing closure and optimization of high-performance digital IP.</li><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Collaborate with verification teams to ensure implementations meet architectural and microarchitectural intent.</li><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Partner with Physical Design (PD), Design for Test (DFT), and other engineering teams to evaluate and optimize design tradeoffs.</li><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Provide technical leadership through mentorship, collaboration, and teamwork.</li></ul> Qualifications Required/minimum qualifications<ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Aptos, sans-serif;">Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.</li></ul> Other Requirements: <ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. </li></ul><ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Aptos, sans-serif;">This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. </li></ul> Additional or Preferred Qualifications <ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">15+ years of experience in logic design delivering complex solutions </li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">10+ years of experience in one or more of the following – floating point arithmetic and datapath design, DMA design, subsystem designs/integration, or custom logic design </li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">5+ years of experience leading logic design teams </li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Multiple successful ASIC tape outs in deep sub-micron technologies </li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Experience with scripting languages such as Python or Perl </li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Experience debugging designs as well as simulation environment </li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Knowledge of verification principles, testbenches, UVM, and coverage </li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Experience working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs </li><li style="margin-bottom: 0in; line-height: normal; margin-top: 0in; margin-right: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Working knowledge of writing assertions, coverage and formal verification </li></ul> #SCHIE Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: <a href="https://careers.microsoft.com/us/en/us-corporate-pay">https://careers.microsoft.com/us/en/us-corporate-pay</a> This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. <hr> Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about <a href="https://careers.microsoft.com/v2/global/en/accessibility.html">requesting accommodations.</a>