Power Delivery Integration and Power Rail Stress Engineer- SoC Power Thermal Performance Validation Engineer (Temporary position)

Job Details:

Job Description:

As a SoC Power Thermal Performance Validation and Optimization Engineer, you will play an essential role in ensuring Intel's products achieve optimal power, thermal, and performance benchmarks at the system-on-chip (SoC) level.

In this position, you will develop and execute validation methodologies, optimize hardware/software solutions, and perform SoC-level debugging to address power, thermal, and performance challenges. Your contribution will directly impact Intel's ability to deliver competitive, high-performing products to market.

This is a Temporary position (12 months)

Key Responsibilities

- Develop and execute System-on-Chip (SoC)-level power delivery, Power Rails Stress (PRS), maximum current (ICCmax), current transient (di/dt), minimum/maximum voltage (Vmin/Vmax), Digital Linear Voltage Regulator (DLVR)/Fully Integrated Voltage Regulator (FIVR), and concurrency plans, including feasibility study and design/verification/simulation of the Power Distribution Network (PDN) and sign-off of IR-drop/Electromigration (IR/EM) metrics, across Intel products.
- Collaborate with architecture, design, firmware, software, Power Management architects, and layout teams to ensure power delivery meets competitive targets and specifications and to define and implement power gating solutions.
- Establish and execute methodologies for validating hardware/software optimizations and to converge the design on all Power Distribution Network (PDN) metrics, ensuring alignment with business Key Performance Indicators (KPIs).
- Perform System-on-Chip (SoC)-level debug to identify root causes and resolve functional and triage failures related to power delivery, on-die power grid/network, thermal, and performance.
- Configure and set up data loggers to collect and analyze power/thermal data, and work with the package integration team to ensure the complete IP system meets the design specification.
- Develop and maintain validation infrastructure (performance monitors, behavioral checkers, and testing environments) and work with the post-silicon debug team to triage, debug, and fix potential Power Distribution Network (PDN) issues.
- Produce comprehensive validation reports summarizing activities and results and communicate findings effectively with relevant teams.
- Drive continuous improvements to validation strategies, methodologies, and processes.

The ideal candidate should show the following behavioral traits

- Strong analytical and problem-solving skills.
- Effective communication and documentation skills for cross-functional collaboration.
- Advanced teamwork to work across teams in multi-faceted groups (architecture, design, verification, firmware, software, and platform teams).

Qualifications:

Minimum qualifications , you must possess the below minimum qualifications to be initially considered for this position.

- Bachelor’s degree in Electronics, Electrical, Computer Engineering, or related field.
- 1+ years of experience in System-on-Chip (SoC) power and performance validation and/or digital logic and optimization.
- 1+ years of experience developing and / or optimization of power/performance Key Performance Indicators (KPIs) and/or circuit design trade-off for power, performance, and area.
- Intermediate to advanced English level.

Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

- A master's degree is preferred.
- Debugging experience for System-on-Chip (SoC)-level power, thermal, and performance failures.
- Power Delivery design, implementation, and validation of high-performance and low-power designs.
- Knowledge of hardware/software optimizations for power and performance.
- Low power implementation techniques.
- Experience with System-on-Chip (SoC)-level debug using Joint Test Action Group (JTAG) debuggers.
- Familiarity with validation tools such as data acquisition/loggers, behavioral checkers, and state space coverage techniques.
- Familiar with system board design/debugging and usage of lab equipment like Oscilloscope and Logic analyzer.
- Experience with Power Delivery Integrity (PDI) validation infrastructure setup.
- Experience with Python Programming language.

Requirements may be met through a combination of relevant industry experience, internship experience, and/or academic work, coursework, or research. Candidates who have completed their degree and whose professional experience is limited to internships may also be considered.

## Job Type:
Intel Contract Employee

## Shift:
Shift 1 (Mexico)

## Primary Location:
Mexico, Guadalajara

Additional Locations:

## Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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## Position of Trust
N/A

Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.