About this role
MediaTek Egypt is seeking a skilled and motivated digital design engineer to join our high-performance team focusing on SerDes and high-speed interface IP development. The successful candidate will be responsible for the architecture, RTL design, and integration of PHY IP blocks, collaborating with cross-functional teams to ensure high-quality and robust IP solutions for cutting-edge SoCs.
Key Responsibilities:
1. PHY IP Architecture Planning
Contribute to the architectural design of PHY IPs for high-speed interfaces such as Ethernet SerDes, USB, PCIe, HDMI, DisplayPort, MPHY, and CPHY.
2. RTL Design & Coding
Develop and implement RTL code for PHY IPs with a focus on performance, power efficiency, and silicon area optimization.
3. Front-end and Back-end Integration
Handle the integration of PHY IPs in both front-end and back-end design flows, ensuring seamless connectivity and function within the SoC.
4. Cross-functional Collaboration
Work closely with MAC design and Design Verification (DV) teams for system-level IP verification.
Collaborate with analog design teams for PHY/SerDes co-simulation and mixed-signal integration.