Sr. ASIC RTL Design Engineer, Memory Controller

Tesla’s AI Hardware team designs the custom silicon that runs Full Self-Driving, trains our neural nets at fleet scale, and will power Optimus. Memory is the bottleneck. Vehicle inference SoCs must deliver high bandwidth at automotive power and thermal limits. Training and AI accelerators must move terabytes per second with HBM. You will own the memory controller RTL that makes that possible.
You will define micro-architecture, write production RTL, close PPA, and debug silicon for LPDDR, GDDR, and/or HBM controllers on Tesla’s next-generation ASICs. The work ships in cars, robots, and our training cluster.

- Own memory controller micro-architecture and RTL from spec through tape-out and silicon bring-up
- Implement JEDEC-compliant controller logic for current DRAM generations: LPDDR5X / LPDDR6, GDDR7, and/or HBM4E
- Design axi/CHI interface, command scheduling, bank/rank/channel arbitration, QoS, refresh, power-state machines, and read/write turnaround under mixed AI, and real-time traffic
- Own the DFI (or equivalent) controller–PHY interface, including training, calibration, and PHY timing constraints
- Drive bandwidth, latency, power, and area with data — not guesswork. Close the loop through synthesis, STA, and silicon measurements
- Deliver synthesis-ready SystemVerilog that passes lint, CDC/RDC, DFT, and low-power (UPF) checks. Partner with physical design on floorplan, congestion, and timing
- Work with architecture, PHY, verification, firmware, and post-silicon teams to close protocol, performance, and reliability issues
- Support FPGA/emulation, first-silicon bring-up, and production debug of the memory interface
- Write micro-architecture specs and timing documentation that other teams can execute against
- Help define Tesla’s next-generation controllers for LPDDR6, GDDR7, and HBM4, including ECC, RAS, and automotive-grade reliability

- Degree in Electrical Engineering, Computer Engineering, or equivalent experience
- 5+ years of RTL design on complex digital IP, with direct ownership of a memory controller or high-speed memory/interface controller
- Hands-on design experience with at least one current DRAM technology, and working knowledge of the others: LPDDR5 / LPDDR5X (LPDDR6 preferred); GDDR6 / GDDR6X (GDDR7 preferred); HBM2E / HBM3 / HBM3E (HBM4 preferred)
- Deep understanding of DRAM internals: banks, ranks, channels, row/column timing (tRCD, tRP, tRAS, tRFC, tCCD, tWTR, tRTW), refresh, and page policy
- Proven scheduler/arbitration and QoS work under high-bandwidth, many-outstanding, mixed-priority traffic
- Proficiency in SystemVerilog/Verilog and scripting (Python, Perl, or Tcl)
- Experience with AMBA host interfaces (AXI, ACE, CHI) or equivalent SoC fabrics
- Experience with synthesis, STA, CDC, lint, and low-power design
- Strong waveform-level debug in simulation, emulation, or silicon