[2027 Campus Hire] Memory Design Automation – Memory Compiler

• Responsible for cutting edge technology node’s SRAM compiler design and deliver best quality of design kit.
• Seamlessly collaborate with SRAM design and layout team to achieve highest quality of design kit delivery.
• Responsible for data analysis and platform development of memory usage big data.
• Responsible for physical verification (DRC/ERC/LVS/ANT/PERC) on SRAM compiler.
• Responsible for spice simulation on timing, power and noise on SRAM compiler.
• Responsible for QA check and development on SRAM compiler.

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