About this role
We are looking for a highly motivated Senior Digital Verification Engineer with 5-7 years of experience in ASIC/SoC verification. The ideal candidate will have strong expertise in System Verilog (SV) and UVM , along with hands-on experience in developing scalable verification environments, coverage-driven verification, and debugging complex RTL and gate-level issues. Exposure to Gate-Level Simulation (GLS) is a plus
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- Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
- 5-7 years of hands-on experience in Digital/ASIC/SoC Verification.
- Strong expertise in: System Verilog (Mandatory) and UVM (Mandatory)
- Familiarity with industry-standard simulators such as Xcelium and Questa.
- Verification experience with some or all protocols such I2C, AHB/APB, MIPI
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