Principal AI Back-End Network Systems Lead

<b>Overview</b><br><div><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;">Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and is responsible for powering Microsoft's Intelligent Cloud mission. SCHIE delivers the core infrastructure and foundational technologies that support Microsoft Azure and other online services globally. Our focus is on smart growth, high efficiency, reliability, and a trusted experience for customers and partners worldwide. </span></p></div><div><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;">The Platform Systems Engineering (PSE) team is seeking a <strong>Principal AI Back-End Network Systems Lead</strong> to serve as the technical lead and end-to-end product development owner for Back End Network across both scale-up and scale-out. The role will lead the product from requirements and architecture through design, integration, validation, manufacturing readiness, deployment, and fleet learning - spanning silicon, network adapters, switches, interconnects, optics/electrical channels, and the fabric as a complete system. </span></p></div><div><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;">The successful candidate will bring deep expertise in one or more AI/ML scale-up or scale-out networking domains and the product-level thinking to connect decisions across the full system. This lead will work from physical and data-link technologies through network and transport behavior to collectives, workloads, modeling, observability, and datacenter deployment, creating clarity across architecture, execution, quality, performance, reliability, power, cost, and schedule. </span></p></div><div><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10.0pt;">#azure #MAIA #AI/ML #Networking #ScaleUp #ScaleOut </span></p></div><br><br><b>Responsibilities</b><br><div><div><p><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><strong>End-to-End Product Ownership &amp; Architecture </strong></span></p></div><div><ul><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Own the Back End Network product definition and execution plan across scale-up and scale-out, from customer/workload needs and product requirements through architecture, development, qualification, deployment, and fleet learning. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Translate AI training and inference requirements into measurable system targets for bandwidth, latency, scale, collective efficiency, reliability, availability, serviceability, power, thermal behavior, cost, security, and schedule. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Make and drive cross-system architecture decisions, interface contracts, feature priorities, and risk tradeoffs; maintain clear ownership, milestones, entry/exit criteria, and product readiness metrics. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Lead NUDD (new, unique, different, and difficult) technology assessments, prototypes, make/buy/partner decisions, and mitigation plans for the highest product risks. </span></li></ul></div><div><p><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><strong>Scale-Up/Scale-Out Systems, Silicon, Switch &amp; Fabric </strong></span></p></div><div><ul><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Lead architecture and integration across accelerator and networking silicon, NICs/DPUs, PHYs/retimers, switch ASICs, switches, cables/backplanes, optics, and fabric topology. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Define scalable scale-up and scale-out architectures, including topology, radix, reach, link speeds, routing, path diversity, oversubscription, failure domains, and resiliency. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Drive silicon, board, switch, firmware, network operating system, and fabric requirements so that components operate as one high-performance and serviceable product. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Partner with silicon, switch, optical, cable, connector, system, manufacturing, and supplier teams to deliver designs from concept through production and datacenter integration. </span></li></ul></div><div><p><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><strong>Optical/Electrical &amp; Cross-Layer Integration</strong> </span></p></div><div><ul><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Oversee electrical and optical technologies for high-speed links, including signal integrity, SerDes/PHY, link training, FEC, reach, power, thermal, mechanical, manufacturability, and interoperability tradeoffs. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Drive end-to-end behavior across the relevant OSI layers - physical, data link, network, and transport - and the system/runtime interfaces above them. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Define and validate Ethernet/RDMA or other scale-up/scale-out protocol behavior, including flow control, congestion control, QoS, routing, packet loss/recovery, telemetry, and security. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Ensure hardware, firmware, drivers, network operating systems, management software, orchestration, and datacenter operations are aligned to common specifications and concepts of operation. </span></li></ul></div><div><p><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><strong>Collectives, Workloads, Modeling &amp; Performance </strong></span></p></div><div><ul><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Connect network architecture to distributed AI workloads, parallelism strategies, traffic patterns, and collective operations such as all-reduce, all-gather, reduce-scatter, and all-to-all. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Establish analytical and simulation models for topology, bandwidth, latency, congestion, failure behavior, collective efficiency, workload scaling, power, and cost. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Use models, emulation, prototypes, and lab/fleet data to predict bottlenecks, guide design choices, set performance budgets, and validate architectural assumptions. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Partner with workload, collective-communication, compiler/runtime, and application teams to co-optimize the network and improve job completion time and cluster efficiency. </span></li></ul></div></div><div><div><p><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><strong>Validation, Reliability, Deployment &amp; Operations </strong></span></p></div><div><ul><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Own the end-to-end validation strategy covering functionality, interoperability, performance, scale, stress, resiliency, reliability, security, serviceability, and upgrade/recovery behavior. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Lead bring-up and root-cause analysis across silicon, electrical/optical links, switch, fabric, protocol, system software, collective, and workload layers using telemetry, packet captures, counters, diagnostics, and lab characterization. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Define production qualification, manufacturing test, deployment, monitoring, rollback, and fleet-health requirements; use operational learning to drive corrective actions and next-generation improvements. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Drive product readiness reviews and ensure the solution can be safely and repeatably deployed, operated, serviced, and scaled in hyperscale datacenters. </span></li></ul></div><div><p><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><strong>Technical Leadership &amp; Ecosystem Execution </strong></span></p></div><div><ul><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Create clarity and technical alignment across architecture, silicon, hardware, optics, firmware, networking, software, validation, manufacturing, datacenter, and workload teams. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Influence internal roadmaps and external partners, including silicon, switch, optical, interconnect, ODM/OEM, and open-source ecosystems; resolve cross-team gaps and ambiguous ownership. </span></li><li style="font-size: 10pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10pt; font-family: arial, helvetica, sans-serif;">Communicate product status, architectural decisions, risks, tradeoffs, and executive asks clearly while mentoring engineers and raising the quality of end-to-end systems engineering. </span></li></ul></div></div><br><br><b>Qualifications</b><br><div><h4><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Required Qualifications</span></h4><ul style="list-style-type: disc;"><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 7+ years technical engineering experience </span><ul style="list-style-type: disc;"><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 8+ years technical engineering experience </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">OR equivalent experience</span></li></ul></li></ul><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><strong>Other Requirements:</strong></span></p><ul style="list-style-type: disc;"><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:</span><ul style="list-style-type: disc;"><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.</span></li></ul></li></ul><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><strong>Preferred Qualifications:</strong></span></p></div><div><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 10+ years of relevant experience in networking, distributed systems, accelerator platforms, or cloud infrastructure</span><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"> or equivalent experience. </span></li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">6+ years of experience designing, developing, integrating, or validating networking for AI/ML, HPC, accelerator, or large-scale cloud systems. </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Deep hands-on expertise in at least one AI/ML networking domain, such as scale-up interconnects and silicon/SerDes/PHY, electrical or optical connectivity, switch systems, scale-out Ethernet/RDMA fabrics, transport/congestion control, collective communication, or workload/fabric performance. </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Demonstrated experience leading a complex hardware/software product or subsystem through requirements, architecture, development, integration, validation, and production deployment. </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Experience architecting or delivering both scale-up and scale-out networks for large AI training or inference systems. </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Experience with high-speed electrical and optical technologies, SerDes/PHY, FEC, signal integrity, link training, retimers, cable/backplane design, pluggable or co-packaged optics, and 400G/800G or faster links. </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Experience with switch ASICs and systems, NICs/DPUs, Ethernet, RDMA/RoCE, routing, QoS, ECN/PFC/DCQCN or related congestion-control methods, SONiC/Linux networking, and network operating systems. </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Understanding of collective communication libraries and operations, distributed training parallelism, AI workload traffic patterns, and workload-driven network optimization. </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Experience with network and system modeling, simulation, emulation, performance analysis, topology studies, traffic generation, or collective/workload scaling analysis. </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Experience developing automated validation, stress, reliability, interoperability, telemetry, diagnostics, observability, and fleet-health frameworks. </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Track record of system bring-up and cross-layer debug from physical links through protocol, runtime, collectives, and application behavior. </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Experience driving manufacturing readiness, supplier/partner execution, datacenter deployment, serviceability, and fleet operations for hardware-intensive products. </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Strong product judgement, technical leadership, collaboration, written communication, and executive presentation skills. </span></li></ul></div><div> </div> <br><br><p>Hardware Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. </p><p></p> <p>Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:<br><a href="https://careers.microsoft.com/us/en/us-corporate-pay">https://careers.microsoft.com/us/en/us-corporate-pay</a></p><br><p>This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.</p><br><hr><br><p>Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about <a href="https://careers.microsoft.com/v2/global/en/accessibility.html"><b><u>requesting accommodations.</u></b></a></p>