Silicon Micro-Architecture and RTL Lead, Google Cloud

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU technology that powers Google's most demanding AI/ML applications. You will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You will contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Minimum qualifications:

- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

- 10 years of experience in Application-Specific Integrated Circuit/System on a chip (ASIC/SoC) development with Verilog/SystemVerilog.

- Experience in micro-architecture and design of IPs and Subsystems.

- Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:

- Experience with programming languages (e.g., Python, C/C++ or Perl).

- Experience in SoC designs and integration flows.

- Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies.

- Knowledge of high performance and low power design techniques.

- Drive development of Complex IPs and Subsystems along with a team of engineers in the Bangalore design organization.

- Own microarchitecture and implementation of IPs and subsystems.

- Work with Architecture, Firmware (FW) and Software (SW) teams to drive feature closure and develop microarchitecture specifications.

- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.

- Identify and drive Power, Performance and Area improvements for the domains owned.