Student Intern - Research

Join us as an Intern with Nokia Bell Labs in Bangalore . The Bell Labs Platform ASIC Research lab explores advanced computing architectures and algorithms for next-generation communication systems. In this internship, you will focus on enabling energy-efficient AI and wireless communication workloads through hardware-aware AI algorithms, neuromorphic computing, and domain-specific hardware acceleration, with potential exploration of RISC-V-based accelerators. You will work across AI/ML, wireless signal processing, energy-efficient computing, and hardware/software co-design, developing concepts and running experiments in Python and C. The work may also involve evaluating compute and energy-efficiency trade-offs and contributing to Verilog-based implementations, accelerator microarchitecture, or architecture design studies. You will work closely with Nokia Bell Labs researchers on early-stage research that could influence future intelligent and energy-efficient wireless systems.

You have

- Enrolled in a   Ph.D. or MS Research program   at the time of the internship.
- Strong background in one or more areas such as computer architecture, VLSI/digital design, AI/ML algorithms, wireless communications, signal processing, embedded systems or hardware/software co-design
- Hands-on programming experience in   Python   and/or   C.
- Ability to design experiments, analyze results, and iterate on research ideas independently.
- Strong fundamentals in algorithms, digital systems, and performance/energy trade-off analysis.
- Availability for a   6-month internship.

It would be nice if you also have

- Exposure to   RISC-V architecture, instruction-set extensions, accelerator design, or processor microarchitecture.
- Interest or experience in   neuromorphic computing, spiking neural networks, event-driven compute, or low-power AI.
- Familiarity with energy-efficient computing techniques such as quantization, sparsity, approximate computing, pruning, or workload-specific acceleration.
- Understanding of   RTL design, hardware simulation, or FPGA/ASIC design flows.