About this role
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Artificial intelligence will be one of humanity’s most transformative inventions. At Google DeepMind, we are a pioneering AI lab with exceptional interdisciplinary teams focused on advancing AI development to solve complex global challenges and accelerate high-quality product innovation for billions of users. We use our technologies for widespread public benefit and scientific discovery, ensuring safety and ethics are always our highest priority.
We are pushing the boundaries across multiple domains. Our global teams offer varied learning opportunities and career pathways for those driven to achieve exceptional results through collective effort.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $217000 - $236000 (USD) + 15% bonus target
Learn more about benefits at Google (https://www.google.com/about/careers/applications/benefits/).
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years or more of experience in ASIC physical verification, including experience with production chips.
- Experience in successful tape-outs of chips at different levels of hierarchy from block to subchips and chip-top.
- Experience with industry-standard Electronic design automation (EDA) tools for physical verification (e.g., Siemens Calibre, Synopsys ICV and Fusion Compiler, Cadence Innovus).
- Software development experience in programming languages (e.g., Python, C++, Go).
Preferred qualifications:
- Experience performing technical physical evaluations of vendors, process nodes and IP.
- Lead and actively contribute to the automation and integration of physical verification (DRC, ANT, LVS, ERC DFM, MIM-Cap design, chip-floorplanning and integration, IP integration, etc) in our automated flow.
- Create a 'correct by construction' methodology from design planning and floorplan.
- Plan and implement pad-rings, Bumps, RDL and IP integration (memories, IO's and analog IPs).
- Collaborate with physical design, circuits, technology, and package leads as a physical design verification engineer, and drive the overall sign-off physical convergence for high-performance designs.
- Leverage your hardware expertise to develop the software components required for physical verification automation, and their software integration in our automated flow.