About this role
<b>Overview</b><br><p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;font-family:arial, helvetica, sans-serif">Microsoft Silicon and Cloud Hardware Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Skype, OneDrive, and the Microsoft Azure platform globally with its server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering trusted experience to customers and partners worldwide, and we are looking for a <strong>Firmware Engineer</strong> to help achieve that mission.</span></p><p style="margin:0.0in;line-height:normal;font-size:11.0pt;font-family:Calibri, sans-serif"> </p><p style="margin:0.0in 0.0in 8.0pt;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-family:arial, helvetica, sans-serif"><span style="font-size:10.0pt;line-height:107%">The Microsoft Azure team is seeking a experienced <strong>Firmware Engineer</strong> for, development, debugging, and validation of next-generation firmware solutions for Microsoft AI accelerators and cloud silicon platforms. </span><span style="font-size:10.0pt;line-height:107%">This role is focused on the design, development , debug and deployment of silicon firmware libraries focused on Compute Domains and High bandwidth memory solutions. This will require experience and very good understanding of SoC architecture, low-level firmware, silicon bring-up, hardware/software co-design, and platform initialization flows. The candidate will own multiple IP’s or sub systems developing IP Firmware library collaborating across multiple with hardware architects, validation engineers, security and Platform firmware and software teams.</span></span></p><p style="margin:0.0in 0.0in 8.0pt;line-height:107%;font-size:11.0pt;font-family:Calibri, sans-serif"><span style="font-size:10.0pt;line-height:107%;font-family:arial, helvetica, sans-serif">#SCHIE</span></p><br><br><b>Responsibilities</b><br><ul><li style="line-height: 107%; font-size: 11.0pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: arial, helvetica, sans-serif;">Design and develop firmware Silicon firmware libraries for HBM ,Compute, and SoC infrastructure subsystems.</span></li><li style="line-height: 107%; font-size: 11.0pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: arial, helvetica, sans-serif;">Work closely with silicon architects during specification and design phases.</span></li><li style="line-height: 107%; font-size: 11.0pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: arial, helvetica, sans-serif;">Develop scalable and maintainable firmware frameworks and APIs.</span></li><li style="line-height: 107%; font-size: 11.0pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: arial, helvetica, sans-serif;">Participate and be responsible for their IP libraries Firmware first-silicon bring-up activities.</span></li><li style="line-height: 107%; font-size: 11.0pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: arial, helvetica, sans-serif;">Debug and root-cause analysis for firmware, hardware, performance, and validation issues.</span></li><li style="line-height: 107%; font-size: 11.0pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: arial, helvetica, sans-serif;">Define firmware verification requirements and test plans.</span></li><li style="line-height: 107%; font-size: 11.0pt; font-family: arial, helvetica, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: arial, helvetica, sans-serif;">Validate Silicon firmeare libraries in pre -silicon simulation and emulation platforms.</span></li></ul><br><br><b>Qualifications</b><br><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><strong>Required Qualifications:</strong></span></p><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience </span><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience </span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">OR equivalent experience. </span></li></ul></li></ul><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><strong>Other Requirements:</strong></span></p><ul style="list-style-type: disc;"><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:</span><ul style="list-style-type: disc;"><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.</span></li></ul></li></ul><p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><strong>Preferred Qualifications:</strong></span></p><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Bachelor's or Master's degree in Computer Science, Electronics Engineering, Electrical Engineering, or a related technical field.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">3–5 years of hands-on expertise in firmware development, embedded systems, or System-on-Chip (SoC) development.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Strong understanding of memory and I/O subsystems within server-class SoC architectures.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Proven ability to develop silicon or firmware IP and platform firmware solutions.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Demonstrated ownership of the end-to-end firmware development lifecycle, from design and implementation through validation and production delivery.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Proficiency in C/C++ and Python programming, with a focus on developing robust, efficient, and scalable firmware.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Solid foundation in bootloader design, platform initialization sequences, and silicon abstraction layers.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Technical knowledge of network controllers and high-performance computing subsystems.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Hands-on involvement in silicon bring-up, debugging, and root-cause analysis using JTAG, Lauterbach TRACE32, and other industry-standard debugging tools.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Familiarity with pre-silicon validation platforms, including ZeBu, FPGA, and VHS.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Knowledge of Azure hardware platforms and their underlying architectures.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Understanding of AI accelerator silicon and associated firmware requirements.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Background in confidential computing, security firmware, and hardware-based security technologies.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Proficiency with hardware emulation platforms such as ZeBu, HAPS, Palladium, and Veloce.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Ability to optimize firmware performance, implement telemetry solutions, and troubleshoot complex system-level issues.</span></li><li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Working knowledge of Reliability, Availability, and Serviceability (RAS) architecture and design principles.</span></li></ul><p style="margin: 0.0in 0.0in 8.0pt; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"> </p> <br><br><p>Firmware Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year. </p><p></p> <p>Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:<br><a href="https://careers.microsoft.com/us/en/us-corporate-pay">https://careers.microsoft.com/us/en/us-corporate-pay</a></p><br><p>This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.</p><br><hr><br><p>Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about <a href="https://careers.microsoft.com/v2/global/en/accessibility.html"><b><u>requesting accommodations.</u></b></a></p>