About this role

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, Verification and Validation team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior SoC HW (Analog/Functional) Validation Engineer to join the team. Responsibilities The Compute Silicon & Manufacturing Engineering (CSME)’s Cloud Compute Development Organization (CCDO) is seeking a Senior SoC HW (Analog/Functional) Validation Engineer to join the post-silicon validation (functional and/or power/performance) team for our projects. This team will be involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner. As a technical individual contributor in this high impact role on the team, you will:<ul style="margin-bottom: 0.0in; margin-top: 0.0px;"><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Calibri, sans-serif;">Own post-silicon validation of one of the following areas PLL, IO electrical/analog or functional IO interfaces.</li><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Calibri, sans-serif;">Define, guide, and contribute to the implementation of silicon debug tools and capabilities.</li><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Calibri, sans-serif;">Become an expert on the overall architecture, implementation of high-speed IO interfaces (PLL, PCI, CXL, etc.) and their interactions with other parts of the SoC, with the platform, and with software.</li><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Calibri, sans-serif;">Provide technical guidance, coaching, and mentorship to other engineers in your areas of expertise.</li><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Calibri, sans-serif;">Develop validation strategy, requirements, environments, tools, and methodologies including debug board and hardware/software requirements.</li><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Calibri, sans-serif;">Apply your knowledge of validation principles and techniques and your judgement to write test plans and implement them by developing test content, scripts, tools and other validation collateral.</li><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Calibri, sans-serif;">Execute content in post-silicon, triage and debug failures.</li><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Calibri, sans-serif;">Apply your growth mindset to learn and adapt in a complex and dynamic environment.</li><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Calibri, sans-serif;">Engage with partners to drive continuous improvement to the design, to validation plans/collateral, and methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably.</li><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Calibri, sans-serif;">Apply your One Microsoft mentality to collaborate with and influence architects, logic designers, verification engineers, other post-silicon validators, and IP and tool providers.</li><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Calibri, sans-serif;">Delight your customers by providing high quality results on schedule.</li><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Calibri, sans-serif;">Provide technical leadership with respect and integrity. </li><li style="margin: 0in 0in 0in 0px; line-height: normal; font-size: 12pt; font-family: Calibri, sans-serif;">Apply your expertise towards pre-silicon verification plans, tests, and debug of your area.</li></ul> We will only achieve our mission if we live our culture. We start with becoming learners in all things—having a growth mindset. Then we apply that mindset to learning about our customers, being diverse and inclusive, working together as one, and—ultimately—making a difference in the world. Qualifications Required Qualifications:<ul><li style="font-size: 11pt; font-family: Calibri, sans-serif; line-height: 107%;">Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.</li></ul> Other Requirements:<ul style="list-style-type: disc;"><li style="font-family: verdana, geneva, sans-serif;">Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: <ul style="list-style-type: disc;"><li style="font-family: verdana, geneva, sans-serif;">Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. </li></ul></li><li style="font-family: verdana, geneva, sans-serif;">This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.</li></ul> Preferred Qualifications:<ul><li style="font-size: 12pt; font-family: 'Times New Roman', serif;">Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. </li><li style="font-size: 12pt; font-family: 'Times New Roman', serif;">Applied understanding of Computer Architecture and CPU/SoC validation principles, including: Understanding of SoC subsystem, SoC system level, and platform level functionality and writing scripts/software with industry standard languages like Python or C/C++.</li><li style="font-size: 12.0pt; font-family: 'Times New Roman', serif;">Proficient communication, collaboration and teamwork skills and ability to lead, grow, and contribute to diverse and inclusive teams.</li><li style="font-size: 12.0pt; font-family: 'Times New Roman', serif;">Verification, logic development, analog validation, or validation tools experience as part of a CPU, SoC and/or IP development team</li><li style="font-size: 12.0pt; font-family: 'Times New Roman', serif;">Demonstrated leadership skills</li><li style="font-size: 12.0pt; font-family: 'Times New Roman', serif;">Demonstrated validation expertise in one or more of the following:<ul style="list-style-type: circle; margin-top: 0.0in; margin-bottom: 0.0in;"><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: Calibri, sans-serif;">Validation of:<ul style="list-style-type: square; margin-top: 0.0in; margin-bottom: 0.0in;"><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: Calibri, sans-serif;">Electrical: Serdes, IO, high speed interconnect, analog circuits</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: Calibri, sans-serif;">Power and Performance</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: Calibri, sans-serif;">Automation, Content Creation, or Tools/Scripts Development</li></ul></li></ul></li></ul><ul style="margin-bottom: 0.0in; margin-top: 0.0px;"><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: Calibri, sans-serif;">Ability to develop synthetic SoC validation Core, Coherency, Memory, and IO content to run on both bare metal and OS environments.</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: Calibri, sans-serif;">Ability to develop sophisticated tools/scripts to support SoC validation debug activities such as maximum power, current transients, and register dumps.</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: Calibri, sans-serif;">Understanding of board level schematics.</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: Calibri, sans-serif;">Understanding system level software and firmware.</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: Calibri, sans-serif;">Experience running silicon content on pre-silicon platforms such as emulation or FPGA.</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: Calibri, sans-serif;">Demonstrated success in hardware/software debug efforts.</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: Calibri, sans-serif;">Hands on expertise debugging silicon failures using on chip debug features (like trace or JTAG) as well as test equipment (like oscilloscopes, protocol analyzers, bit error rate testers, logic</li></ul> #SCHIE #CSME Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: <a href="https://careers.microsoft.com/us/en/us-corporate-pay">https://careers.microsoft.com/us/en/us-corporate-pay</a> This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. <hr> Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about <a href="https://careers.microsoft.com/v2/global/en/accessibility.html">requesting accommodations.</a>