About this role

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Senior SoC HW (Power & Performance) Validation Engineer to help achieve that mission.The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow, the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Verification & Validation team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Senior SoC HW (Power & Performance) Validation Engineer with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior SoC HW (Power & Performance) Validation Engineer to join the team to support our mission and culture. This key role will impact the organization by delivering an optimized and tuned system to the customer. Responsibilities The candidate for this position will be expected and able to complete the following responsibilities:<ul><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Own the post-silicon Power & Performance validation strategy and execution, including performance, power, thermal, functional, and electrical characterization across workloads and operating conditions. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Define silicon performance and power characterization methodology across PVT, voltage/frequency operating points, DVFS, power states, and representative system workloads. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Develop and drive performance validation plans covering compute, memory, interconnect, I/O, power management, and system-level workload behavior. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Define, guide, and contribute to silicon debug, telemetry, profiling, and analysis capabilities needed to identify performance bottlenecks, power inefficiencies, and unexpected silicon behavior. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Partner with architecture, design, firmware, OS, verification, platform, and workload teams to translate product performance and power goals into measurable post-silicon validation requirements. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Analyze performance, power, and thermal data to identify bottlenecks, regressions, and optimization opportunities, driving issues from detection through root cause and resolution. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Develop validation environments, automation, workloads, benchmarks, tools, scripts, and methodologies needed for efficient Power & Performance characterization and debug. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Execute post-silicon validation and characterization, triage complex cross-layer issues, and correlate behavior across silicon, firmware, OS, platform, and workload layers. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Drive performance-per-watt, workload efficiency, and system-level optimization, partnering with architecture and engineering teams to improve product competitiveness. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Engage with design and verification partners to shift Power & Performance validation left, improving pre-silicon modeling, coverage, correlation, and early issue detection. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Apply experience toward pre-silicon Power & Performance verification, including workload definition, performance modeling, test development, and pre-to-post-silicon correlation. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Drive continuous improvement in validation methodology, automation, telemetry, and analytics to find performance and power issues earlier and accelerate root cause. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Coordinate across multiple organizations on Power & Performance requirements, milestones, dependencies, deliverables, and execution. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Provide technical leadership, coaching, and mentorship in areas such as performance analysis, power management, workload characterization, silicon debug, and validation methodology. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Apply a growth mindset to rapidly learn and adapt as silicon architectures, workloads, firmware, and system requirements evolve. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Demonstrate a One Microsoft mindset, influencing across organizational boundaries and building alignment among architecture, design, verification, firmware, OS, platform, and validation teams. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Deliver high-quality, data-driven Power & Performance results on schedule, enabling product decisions and readiness. </li><li style="line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;">Provide technical leadership with respect, integrity, engineering rigor, and effective customer focus.</li></ul> Qualifications Required Qualifications:<ul><li>Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.</li></ul> Other Requirements:<ul><li>Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. </li><li>This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.</li></ul> Preferred Qualifications:<ul><li>Understanding of SoC system level and platform level functionality, defining silicon validation requirements, writing scripts/software with industry standard languages like Python or C/C++.</li><li>Proficient communication, collaboration and teamwork skills and ability to lead, grow, and contribute to diverse and inclusive teams.</li><li>Verification, logic development, analog validation, or validation tools experience as part of a CPU, SoC and/or IP development team.</li><li>Leadership skills.</li><li>Demonstrated validation expertise in one or more of the following:<ul><li>Validation of:<ul><li>Power validation and Performance testing plus tuning.</li><li>Automation, Content Creation, or Tools/Scripts Development.</li></ul></li></ul></li><li>Ability to develop synthetic SoC validation Core, Coherency, Memory, and IO content to run on both bare metal and OS environments.</li><li>Ability to develop sophisticated tools/scripts to support SoC validation debug activities such as maximum power, current transients, and register dumps.</li><li>Understanding of board level schematics.</li><li>Understanding system level software and firmware.</li><li>Experience running silicon content on pre-silicon platforms such as emulation or FPGA.</li><li>Demonstrated success in hardware/software debug efforts.</li></ul> #SCHIE #CSME Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: <a href="https://careers.microsoft.com/us/en/us-corporate-pay">https://careers.microsoft.com/us/en/us-corporate-pay</a> This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. <hr> Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about <a href="https://careers.microsoft.com/v2/global/en/accessibility.html">requesting accommodations.</a>