About this role

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a SoC Hardware (Power Management) Validation Engineer to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, Verification and Validation team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a SoC Hardware (Power Management) Validation Engineer with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a SoC Hardware (Power Management) Validation Engineer to join the team. Responsibilities The Compute Silicon & Manufacturing Engineering (CSME)’s Cloud Compute Development Organization (CCDO) is seeking a SoC HW Power Management Validation Engineer to join the post-silicon validation team for our projects. This team will be involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner. As a technical individual contributor in this role on the team, you will:<ul><li style="line-height: normal; background-color: white; font-size: 11.0pt; font-family: Calibri, sans-serif;">Own post-silicon validation and debug of Power Management features across CPU cores, mesh, memory, I/O, package, and platform power domains.</li><li style="line-height: normal; background-color: white; font-size: 11.0pt; font-family: Calibri, sans-serif;">Develop and execute comprehensive validation strategies for power states, DVFS, idle and active power management, thermal management, performance-per-watt optimization, and system-level power features.</li><li style="line-height: normal; background-color: white; font-size: 11.0pt; font-family: Calibri, sans-serif;">Drive root-cause analysis of complex silicon, firmware, hardware, and software issues impacting power, performance, stability, and feature readiness.</li><li style="line-height: normal; background-color: white; font-size: 11.0pt; font-family: Calibri, sans-serif;">Define validation requirements, test plans, methodologies, automation frameworks, debug tools, and telemetry solutions to improve validation coverage and efficiency.</li><li style="line-height: normal; background-color: white; font-size: 11.0pt; font-family: Calibri, sans-serif;">Collaborate closely with architects, design, firmware, verification, system software, and platform teams to ensure first-time-right implementation of power management features.</li><li style="line-height: normal; background-color: white; font-size: 11.0pt; font-family: Calibri, sans-serif;">Lead silicon bring-up, feature characterization, workload-based validation, and power-performance correlation activities across development milestones.</li><li style="line-height: normal; background-color: white; font-size: 11.0pt; font-family: Calibri, sans-serif;">Analyze power, performance, and thermal telemetry to identify bottlenecks, validate design assumptions, and optimize platform efficiency.</li><li style="line-height: normal; background-color: white; font-size: 11.0pt; font-family: Calibri, sans-serif;">Influence pre-silicon verification strategies, coverage plans, and debug methodologies using post-silicon learnings.</li><li style="line-height: normal; background-color: white; font-size: 11.0pt; font-family: Calibri, sans-serif;">Provide technical leadership, mentoring, and guidance in Power Management architecture, validation techniques, and debug methodologies.</li><li style="line-height: normal; background-color: white; font-size: 11.0pt; font-family: Calibri, sans-serif;">Drive continuous improvement in validation infrastructure, automation, and debug capabilities to accelerate issue resolution and improve product quality.</li><li style="line-height: normal; background-color: white; font-size: 11.0pt; font-family: Calibri, sans-serif;">Partner across organizations to deliver high-quality silicon on schedule while meeting aggressive performance-per-watt and power efficiency targets.</li><li style="line-height: normal; background-color: white; font-size: 11.0pt; font-family: Calibri, sans-serif;">Foster a collaborative One Microsoft culture through technical excellence, ownership, innovation, and integrity.</li></ul>We will only achieve our mission if we live our culture. We embrace a growth mindset, continuously learn from our customers and partners, foster diversity and inclusion, collaborate as One Microsoft, and strive to make a meaningful impact through technology. Qualifications Required Qualifications:<div><ul><li>Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.</li></ul> Other Requirements:<ul><li style="line-height: 107%; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. </li><li style="line-height: 107%; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. </li></ul></div> Preferred Qualifications:<ul><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">Proficient communication, collaboration and teamwork skills and ability to lead, grow, and contribute to diverse and inclusive teams.</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">Verification, logic development, analog validation, or validation tools experience as part of a CPU, SoC and/or IP development team</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">Leadership skills</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">Demonstrated validation expertise in one or more of the following:<ul style="list-style-type: circle; margin-top: 0.0in; margin-bottom: 0.0in;"><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">Validation of:<ul style="list-style-type: circle; margin-top: 0.0in; margin-bottom: 0.0in;"><li style="line-height: normal; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">Power validation and Performance testing plus tuning.</li><li style="line-height: normal; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">Automation, Content Creation, or Tools/Scripts Development</li></ul></li></ul></li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">Ability to develop synthetic SoC validation Core, Coherency, Memory, and IO content to run on both bare metal and OS environments.</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">Ability to develop sophisticated tools/scripts to support SoC validation debug activities such as maximum power, current transients, and register dumps.</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">Understanding of board level schematics.</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">Understanding system level software and firmware.</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">Experience running silicon content on pre-silicon platforms such as emulation or FPGA.</li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: normal; font-size: 12.0pt; font-family: arial, helvetica, sans-serif;">Demonstrated success in hardware/software debug efforts.</li></ul> #SCHIE #CSME Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: <a href="https://careers.microsoft.com/us/en/us-corporate-pay">https://careers.microsoft.com/us/en/us-corporate-pay</a> This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. <hr> Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about <a href="https://careers.microsoft.com/v2/global/en/accessibility.html">requesting accommodations.</a>