ASIC Engineer, Physical Design CAD

Meta's silicon engineering team is building custom infrastructure silicon to power the compute demands of AI, data center, and next-generation hardware platforms.

The Infra Silicon Implementation CAD team owns the physical design flows and automation that take our designs from RTL handoff through synthesis, place and route, timing closure, and physical signoff. As a Physical Design CAD engineer, you will be responsible for building and owning the flow infrastructure used daily by PD engineers across concurrent tapeout programs. This is a high-leverage role: the automation you build directly determines how quickly a chip organization converges.

Responsibilities

Develop, maintain, and own stages of the digital physical design flow — synthesis, floorplanning and design planning, placement, CTS, routing, extraction, timing ECO, and STA signoff
Build and extend flow automation in Python and Tcl, integrated with Meta’s internal build, job-scheduling, and continuous integration infrastructure
Partner with PD engineers and design leads to debug flow and Quality of Release (QoR) issues on active tapeout programs, and convert recurring workarounds into supported flow features
Qualify and integrate commercial EDA tools, drive issues to resolution with vendor application-engineering teams, and manage tool version migrations across programs
Build constraint and netlist validation capability so design-intent errors are caught in-flow rather than at sign-off
Develop QoR tracking, metrics, and dashboards that give design teams and program leadership visibility into convergence across blocks and subsystems
Write and maintain user-facing flow documentation and training, and support designers as part of a shared on-call rotation
Collaborate with external design partners and foundry or ASIC vendors on flow alignment and design handoff criteria

Qualifications

Bachelor’s or Master’s degree in Electrical or Electronics Engineering, Computer Engineering, and/or equivalent practical experience
2+ years of experience in either ASIC physical design or CAD, including hands-on work with automation, flow development, drafting methodologies, solutions, and/or hands-on work with placement, clock tree synthesis, routing, and timing closure
Experience with digital physical design implementation on advanced process nodes, including synthesis, place and route, and timing closure
Hands-on experience with industry physical design tools, such as Fusion Compiler, Genus, Innovus, PrimeTime, Tempus, or StarRC
Proficiency in Tcl and Python for EDA flow development and automation
Experience debugging flow, timing, or physical verification issues on a production tapeout
Experience with version control and collaborative code review Experience working across geographically distributed teams and with external design partners
Experience with power integrity and EM/IR analysis, and/or physical verification and logic equivalence sign-off
Experience with timing constraint development and validation methodology, including SDC generation and constraint checking
Experience building or owning a production CAD or physical design flow used by multiple design teams
Experience building data pipelines or dashboards for design metrics and QoE analysis
Experience with compute and license capacity management for large EDA workloads
Experience applying AI or LLM-based tooling to engineering workflows
Experience with hierarchical design planning and block-level partitioning on large SoCs