About this role
Lead Block Coordinator (APR / Physical Design) — 10+Yrs (Innovus)
• 10+ years of ASIC/SoC Physical Design / APR experience in a reputed product company, with multiple tapeouts.
• Senior Block Coordinator responsible for planning/execution and closure of 15+ blocks.
• Strong hands-on expertise in Cadence Innovus: floorplan, place/opt, CTS, route, and ECO closure at block level.
• Proven ability to drive timing closure (setup/hold), MMMC, constraints/exceptions alignment, and QoR improvement across blocks.
• Solid experience in congestion/routability debugging (macro placement/pin access/blockages/density) and driving closure actions with clear metrics.
• Experience across advanced and lower/mature nodes (e.g., 2/3/4/6nm).
• Strong understanding of block signoff readiness and coordination for DRC/LVS, SI-aware optimization, and IR/EM closure with signoff teams.
• Mandatory scripting/automation: strong Tcl (Innovus) for flow execution, report parsing, and QoR tracking; Python/Perl/Shell preferred.
• Strong cross-team coordination with STA/DFT/Synthesis/CAD.