About this role
About onsemi
onsemi (Nasdaq: ON) is a global leader in intelligent power and sensing technologies, driving innovation to build a safer, cleaner, and smarter world. With a strong focus on automotive, industrial, and AI data center markets, we are shaping the future of vehicle electrification, sustainable energy, and advanced automation.
About the Treo Platform
The Treo Platform is a cutting-edge analog and mixed-signal solution built on 65nm Bipolar-CMOS-DMOS (BCD) technology. Supporting voltage ranges from 1–90V and operating temperatures up to 175°C, Treo is engineered for high‑performance automotive, medical, industrial, and AI data‑center applications. Its modular architecture simplifies design, reduces system cost, and accelerates time‑to‑market. All products are manufactured at our 300mm fab in East Fishkill, NY.
About the Role
We are seeking an Analog Design Engineer to contribute to the development of power management and clocking analog IP blocks for Treo‑based SoC platforms. This is a hands‑on individual contributor role reporting to the Analog Design Team Manager. You will be responsible for the detailed design, verification, and delivery of high‑quality analog IP, working closely with cross‑functional partners to enable successful product tape‑out and silicon validation.
Qualifications – Minimum
• 10+ years of experience in analog IC design.
• Hands‑on experience designing power management and/or clocking circuits for integrated SoCs.
• Solid understanding of device physics, analog architectures, and layout‑dependent effects.
• Proficiency with SPICE/AMS simulation, variability analysis, and mixed‑signal co‑simulation.
• Ability to work independently on assigned blocks while communicating progress and risks clearly.
Qualifications – Preferred
• Experience with Verilog‑A/AMS/SV RNM modeling or mixed‑signal verification environments.
• Exposure to automotive or industrial reliability and functional‑safety requirements.
• Interest in AI/ML‑assisted design, automation, or design‑space exploration.
Success Metrics
• On‑time delivery of assigned analog IP blocks meeting performance and quality targets.
• First‑pass silicon success for owned blocks with robust PVT coverage.
• Effective collaboration with cross‑functional teams and proactive issue resolution.
• Clear technical growth and increasing ownership across platform generations.