About this role
We are seeking a Senior Analog Design Engineer to develop power management and clocking IP for Treo-based SoCs. This role is a hands-on contributor expected to take ownership of complex analog blocks while collaborating across design, verification, and validation teams.
Qualifications – Minimum
- 5+ years of experience in analog IC design.
- Experience designing power management and/or clocking circuits.
- Solid understanding of analog circuit design, device physics, and layout effects.
- Proficiency with SPICE/AMS simulation and mixed-signal verification.
- Ability to work independently and communicate technical issues effectively.
Qualifications – Preferred
- Experience with Verilog-A/AMS modeling.
- Exposure to automotive or industrial applications.
- Interest in AI-assisted design and automation workflows.